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參數(shù)資料
| 型號： | ISL6545EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 中文描述： | 單5V或12V同步降壓脈寬調(diào)制（PWM）控制器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 302K |
| 代理商： | ISL6545EVAL1 |
www.DataSheet4U.com
9
FN6305.3
November 15, 2006
Application schematic on page 2 for more detail; R
S
is the
upper resistor; R
OFFSET
(shortened to R
O
below) is the
lower one. The recommended value for R
S
is 1 - 5k
Ω
(±1%
for accuracy) and then R
OFFSET
is chosen according to the
equation below. Since R
S
is part of the compensation circuit
(see Feedback Compensation section), it is often easier to
change R
OFFSET
to change the output voltage; that way the
compensation calculations do not need to be repeated. If
V
OUT
= 0.6V, then R
OFFSET
can be left open. Output
voltages less than 0.6V are not available.
Input Voltage Considerations
The Typical Application diagram on page 2 shows a
standard configuration where V
CC
is either 5V (±10%) or
12V (±20%); in each case, the gate drivers use the V
CC
voltage for LGATE and BOOT/UGATE. In addition, V
CC
is
allowed to work anywhere from 6.5V up to the 14.4V
maximum. The V
CC
range between 5.5V and 6.5V is
NOT
allowed for long-term reliability reasons, but transitions
through it to voltages above 6.5V are acceptable.
There is an internal 5V regulator for bias; it turns on between
5.5 and 6.5V; some of the delay after POR is there to allow a
typical power supply to ramp up past 6.5V before the soft-
start ramps begins. This prevents a disturbance on the
output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should
be minimal. So while the recommendation is to not have the
output enabled during the transition through this region, it
may be acceptable. The user should monitor the output for
their application, to see if there is any problem.
The V
IN
to the upper MOSFET can share the same supply
as V
CC
, but can also run off a separate supply or other
sources, such as outputs of other regulators. If V
CC
powers
up first, and the V
IN
is not present by the time the
initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the
V
IN
ramp when it is applied. If this is not desired, then
change the sequencing of the supplies, or use the
COMP/SD pin to disable V
OUT
until both supplies are ready.
Figure 6 shows a simple sequencer for this situation. If V
CC
powers up first, Q1 will be off, and R3 pulling to V
CC
will turn
Q2 on, keeping the ISL6545 in shut-down. When V
IN
turns
on, the resistor divider R1 and R2 determines when Q1 turns
on, which will turn off Q2, and release the shut-down. If V
IN
powers up first, Q1 will be on, turning Q2 off; so the ISL6545
will start-up as soon as V
CC
comes up. The V
DISABLE
trip
point is 0.4V nominal, so a wide variety of NFET’s or NPN’s
or even some logic IC’s can be used as Q1 or Q2; but Q2
must be low leakage when off (open-drain or open-collector)
so as not to interfere with the COMP output. Q2 should also
be placed near the COMP/SD pin.
The V
IN
range can be as low as ~1V (for V
OUT
as low as the
0.6V reference). It can be as high as 20V (for V
OUT
just
below V
IN
). There are some restrictions for running high V
IN
voltage.
The first consideration for high V
IN
is the maximum BOOT
voltage of 36V. The V
IN
(as seen on PHASE) plus V
CC
(boot
voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If V
IN
is
20V, that limits V
CC
plus ringing to 16V.
The second consideration for high V
IN
is the maximum
(BOOT - V
CC
) voltage; this must be less than 24V. Since
BOOT = V
IN
+ V
CC
+ ringing, that reduces to (V
IN
+ ringing)
must be <24V. So based on typical circuits, a 20V maximum
V
IN
is a good starting assumption; the user should verify the
ringing in their particular application.
Another consideration for high V
IN
is duty cycle. Very low
duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
require component selection compatible with that choice
(such as low r
DS(ON)
lower MOSFET, and a good LC output
filter). At the other extreme (for example, 20V in to 12V out),
the upper MOSFET needs to be low r
DS(ON)
. In addition, if
the duty cycle gets too high, it can affect the overcurrent
sample time. In all cases, the input and output capacitors
and both MOSFETs must be rated for the voltages present.
Switching Frequency
The switching frequency is either a fixed 300 or 600kHz,
depending on the part number chosen (ISL6545 is 300kHz;
ISL6545A is 600kHz; the generic name “ISL6545” may apply
to either in the rest of this document, except when choosing
the frequency). However, all of the other timing mentioned
(POR delay, OCP sample, soft-start, etc.) is independent of
the clock frequency (unless otherwise noted).
BOOT Refresh
In the event that the UGATE is on for an extended period of
time, the charge on the boot capacitor can start to sag,
raising the r
DS(ON)
of the upper MOSFET. The ISL6545 has
a circuit that detects a long UGATE on-time (nominal 100μs),
and forces the LGATE to go high for one clock cycle, which
will allow the boot capacitor some time to recharge.
Separately, the OCP circuit has an LGATE pulse stretcher
V
OUT
0.6V
R
---------------------------
R
+
(
)
O
=
R
O
R
0.6V
OUT
----------------–
=
FIGURE 6. SEQUENCER CIRCUIT
R
2
V
IN
R
1
R
3
V
CC
to COMP/SD
Q
2
Q
1
ISL6545, ISL6545A
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