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參數(shù)資料
| 型號： | ISL6556BCB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | PWM Controller with Wide Input Range 8-SOIC -40 to 125 |
| 中文描述： | SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | PLASTIC, MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 692K |
| 代理商： | ISL6556BCB |
19
FN9097.4
December 28, 2004
Current Sensing
The ISEN pins are denoted ISEN1, ISEN2, ISEN3 and
ISEN4. The resistors connected between these pins and the
respective phase nodes determine the gains in the load-line
regulation loop and the channel-current balance loop as well
as setting the overcurrent trip point. Select values for these
resistors based on the room temperature r
DS(ON)
of the
lower MOSFETs; the full-load operating current, I
FL
; and the
number of phases, N using Equation 18 (see also Figure 3).
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistor. When the components of
one or more channels are inhibited from effectively dissipating
their heat so that the affected channels run hotter than
desired, choose new, smaller values of R
ISEN
for the affected
phases (see the section entitled
Channel-Current Balance
).
Choose R
ISEN,2
in proportion to the desired decrease in
temperature rise in order to cause proportionally less current
to flow in the hotter phase.
In Equation 19, make sure that
T
2
is the desired temperature
rise above the ambient temperature, and
T
1
is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 19 is usually
sufficient, it may occasionally be necessary to adjust R
ISEN
two or more times to achieve optimal thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R
FB
in Figure 5.
Its value depends on the desired full-load droop voltage
(V
DROOP
in Figure 5). If Equation 19 is used to select each
ISEN resistor, the load-line regulation resistor is as shown
in Equation 20.
V
6
–
×
If one or more of the ISEN resistors is adjusted for thermal
balance, as in Equation 20, the load-line regulation resistor
should be selected according to Equation 21 where I
FL
is the
full-load operating current and R
ISEN(n)
is the ISEN resistor
connected to the n
th
ISEN pin.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in
Load-Line Regulation
.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
C
and C
C
.
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R
FB
, has already been chosen as
outlined in
Load-Line Regulation Resistor
. Select a target
bandwidth for the compensated system, f
0
. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f
0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
R
ISEN
r
70
10
6
×
)
–
-----------------------
I
--N
=
(EQ. 18)
R
ISEN 2
R
ISEN
T
2
T
1
----------
=
(EQ. 19)
R
FB
70
10
------------------------
=
(EQ. 20)
R
FB
V
I
FL
r
DS ON
)
--------------------------------
R
ISEN n
( )
n
∑
=
(EQ. 21)
FIGURE 12. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6556B CIRCUIT
I
COMP
C
C
R
C
R
FB
FB
VDIFF
-
+
V
DROOP
C
2
(OPTIONAL)
2
π
LC
-------1
f
0
>
R
C
R
FB
2
π
f
V
LC
IN
0.75V
π
V
PP
R
FB
f
0
-------0.75V
=
C
C
2
=
Case 1:
ISL6556B
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