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參數(shù)資料
| 型號(hào)： | ISL6556BCBZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application |
| 中文描述： | SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | LEAD FREE, PLASTIC, MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 692K |
| 代理商： | ISL6556BCBZ-T |
12
FN9097.4
December 28, 2004
pulse width which corrects for any unbalance and drives the
error current toward zero. Figure 4 illustrates Intersil’s
patented current-balance method as implemented on
channel-1 of a multi-phase converter.
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided,
resulting in a cost-effective and easy-to-implement solution
relative to single-phase conversion. Channel-current balance
insures that the thermal advantage of multi-phase
conversion is realized. Heat dissipation in multiple channels
is spread over a greater area than can easily be
accomplished using the single phase approach.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one or two channels may be able to
cool more effectively than the other(s) due to nearby air flow
or heat sinking components. The other channel(s) may have
more difficulty cooling with comparatively less air flow and
heat sinking. The hotter channels may also be located close
to other heat-generating components tending to drive their
temperature even higher. In these cases, the proper
selection of the current sense resistors (R
ISEN
in Figure 3)
introduces channel current unbalance into the system.
Increasing the value of R
ISEN
in the cooler channels and
decreasing it in the hotter channels moves all channels into
thermal balance at the expense of current balance.
Voltage Regulation
The integrating compensation network shown in Figure 5
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6556B to include the
combined tolerances of each of these elements.
The output of the error amplifier, V
COMP
, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 5.
The ISL6556B incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the non-
inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V
DIFF
, is
connected to the inverting input of the error amplifier through
an external resistor.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID12.5. The DAC decodes the 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20
μ
A pull-up to an internal 2.5V
source for use with open-drain outputs. The pull-up current
diminishes to zero above the logic threshold to protect
voltage-sensitive output devices. External pull-up resistors
can augment the pull-up current sources in case leakage
into the driving device is greater than 20
μ
A.
FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
÷
N
I
AVG
I
4
*
I
3
*
I
2
Σ
-
+
+
-
+
-
f(j
ω
)
PWM1
I
1
V
COMP
SAWTOOTH SIGNAL
I
ER
NOTE: *Channels 3 and 4 are optional.
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
I
AVG
EXTERNAL CIRCUIT
R
C
C
C
ISL6556B INTERNAL CIRCUIT
COMP
R
FB
FB
VDIFF
VSEN
RGND
-
+
V
DROOP
ERROR AMPLIFIER
-
+
V
OUT
+
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
V
COMP
REF
TCOMP
R
TCOMP
C
REF
-
+
V
OUT
-
VID DAC
1k
ISL6556B
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