參數(shù)資料
型號: ISL6556BCBZ-T
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application
中文描述: SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO28
封裝: LEAD FREE, PLASTIC, MS-013AE, SOIC-28
文件頁數(shù): 14/24頁
文件大?。?/td> 692K
代理商: ISL6556BCBZ-T
14
FN9097.4
December 28, 2004
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 5, a current proportional to the average
current in all active channels, I
AVG
, flows from FB through a
load-line regulation resistor, R
FB
. The resulting voltage drop
across R
FB
is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
In most cases, each channel uses the same R
ISEN
value to
sense current. A more complete expression for V
DROOP
is
derived by combining equations 4 and 5.
Output-Voltage Offset Programming
The ISL6556B allows the designer to accurately adjust the
offset voltage. When a resistor, R
OFS
, is connected between
OFS and VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (I
OFS
) to flow into OFS. If R
OFS
is connected to ground, the voltage across it is regulated to
0.5V, and I
OFS
flows out of OFS. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product (I
OFS
x
R
FB
). These functions are shown in Figures 6 and 7.
As evident in Figure 7, the OFSOUT pin must be connected
to the FB pin for this current injection to function in
ISL6556BCR. The current flow through R
FB
creates an offset
at the REF pin, which is ultimately duplicated at the output of
the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set R
OFS
:
For Positive Offset (connect R
OFS
to GND):
For Negative Offset (connect R
OFS
to VCC):
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs during regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
V
DROOP
I
AVG
R
FB
=
(EQ. 5)
V
DROOP
I
-----N
r
ISEN
)
-R
FB
=
(EQ. 6)
(EQ. 7)
R
OFS
0.5
OFFSET
R
×
--------------------------
=
(EQ. 8)
R
OFS
2
R
×
OFFSET
--------------------------
=
DYNAMIC
VID D/A
E/A
VCC
OR
GND
FB
OFS
VCC
GND
+
-
+
-
0.5V
2.0V
R
OFS
R
FB
VDIFF
ISL6556BCB
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6556BCB (28-LEAD SOIC)
DYNAMIC
VID D/A
E/A
VCC
OR
GND
FB
OFS
VCC
GND
+
-
+
-
0.5V
2.0V
R
OFS
R
FB
VDIFF
ISL6556BCR
OFSOUT
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6556BCR (32-LEAD QFN)
ISL6556B
相關(guān)PDF資料
PDF描述
ISL6557ACB-T Multi-Phase PWM Controller for Core-Voltage Regulation
ISL6557A Multi-Phase PWM Controller for Core-Voltage Regulation
ISL6557ACB Multi-Phase PWM Controller for Core-Voltage Regulation
ISL6557ACBZ Multi-Phase PWM Controller for Core-Voltage Regulation
ISL6557ACBZ-T Multi-Phase PWM Controller for Core-Voltage Regulation
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