7 FN7803.1 December 23, 2013 Output Rise and Fall Times tOR/t
參數(shù)資料
型號(hào)： ISL76321ARZ
廠商： Intersil
文件頁數(shù)： 12/14頁
文件大?。?/td> 0K
描述： IC VIDEO SERDES LONG 16BIT 48QFN
標(biāo)準(zhǔn)包裝： 260
功能： 串行器/解串器
輸入類型： RGB
輸出類型： 串行
輸入數(shù)： 16
輸出數(shù)： 1
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN（7x7）
包裝： 管件
ISL76321
7
FN7803.1
December 23, 2013
Output Rise and Fall Times
tOR/tOF
Slew rate control set to min
CL = 8pF
1ns
Slew rate control set to max,
CL = 8pF
4ns
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency
fIN
650
MHz
PCLK_IN Duty Cycle
tIDC
40
50
60
%
Parallel Input Setup Time
tIS
3.5
ns
Parallel Input Hold Time
tIH
1.0
ns
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Frequency
fOUT
650
MHz
PCLK_OUT Duty Cycle
tODC
50
%
PCLK_OUT Period Jitter (rms)
tOJ
Clock randomizer off
0.5
%tPCLK
PCLK_OUT Spread Width
tOSPRD
Clock randomizer on
±20
%tPCLK
PCLK_OUT to Parallel Data Outputs
(includes Sync and DE pins)
tDV
Relative to PCLK_OUT,
(Note 9)
-1.0
5.5
ns
Deserializer Output Latency
tCPD
Inherent in the design
4
9
14
PCLK
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time
tPLL
100
s
REF_CLK to PCLK_OUT Maximum Frequency
Offset
PCLK_OUT is the
recovered clock
1500
5000
ppm
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit
VODTR
TXCN = 0x00
650
800
900
mVP-P
TXCN = 0x0F
900
mVP-P
TXCN = 0xF0
1100
mVP-P
TXCN = 0xFF
1300
mVP-P
HS Differential Output Voltage, Non-Transition
Bit
VODNTR
TXCN = 0x00
650
800
900
mVP-P
TXCN = 0x0F
900
mVP-P
TXCN = 0xF0
430
mVP-P
TXCN = 0xFF
600
mVP-P
HS Generated Output Common Mode Voltage
VOCM
2.35
V
HS Common Mode Serializer-Deserializer
Voltage Difference
ΔVCM
10
20
mV
HS Differential Output Impedance
ROUT
80
100
120
Ω
HS Output Latency
tLPD
Inherent in the design
4
7
10
PCLK
HS Output Rise and Fall Times
tR/tF
20% to 80%
150
ps
HS Differential Skew
tSKEW
<10
ps
HS Output Random Jitter
tRJ
PCLK_IN = 45MHz
6
psrms
HS Output Deterministic Jitter
tDJ
PCLK_IN = 45MHz
25
psP-P
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the
operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
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