參數(shù)資料
型號(hào): ISL8484
廠商: Intersil Corporation
英文描述: Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch(超低導(dǎo)通電阻,+1.65V至+4.5V, 單電源, 雙路單刀雙擲模擬開(kāi)關(guān))
中文描述: 超低電阻,從1.65V至4.5V,單電源,雙路SPDT模擬開(kāi)關(guān)(超低導(dǎo)通電阻,從1.65V至4.5V時(shí),單電源,雙路單刀雙擲模擬開(kāi)關(guān))
文件頁(yè)數(shù): 8/15頁(yè)
文件大小: 330K
代理商: ISL8484
8
FN6128.3
June 14, 2007
Detailed Description
The ISL8484 is a bidirectional, dual single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single 1.65V to 4.5V supply with low on-resistance
(0.23
Ω
) and high speed operation (t
ON
= 20ns, t
OFF
= 15ns).
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.65V), low power consumption (4.5
μ
W max), low leakage
currents (110nA max), and the tiny DFN and MSOP
packages. The ultra low ON-resistance and r
ON
flatness
provide very low insertion loss and distortion to applications
that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil
recommends adding a 100
Ω
resistor in series with the V+
power supply pin of the ISL8484 IC (see Figure 8).
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from the
V+ power supply to ground. This will result in a significant
amount of current flow in the IC which can potentially create a
latch-up state or permanently damage the IC. The external V+
resistor limits the current during this over-stress situation and
has been found to prevent latch-up or destructive damage for
many over voltage transient events.
Under normal operation the sub-microamp I
DD
current of the
IC produces an insignificant voltage drop across the 100
Ω
series resistor resulting in no impact to switch operation or
performance.
.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (See
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
Ω
resistor in series with the input (see Figure 9). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low r
ON
switch, so two small signal
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
0V or V+
ANALYZER
V+
C
NO OR NC
SIGNAL
GENERATOR
R
L
GND
IN
1
COM
50
Ω
N.C.
COM
NC or NO
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
V+
C
GND
NO OR NC
COM
IN
IMPEDANCE
ANALYZER
0V OR V+
Repeat test for all switches.
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
IN
COM
100
Ω
NO
NC
V+
GND
C
OPTIONAL
PROTECTION
RESISTOR
ISL8484
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