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參數(shù)資料
| 型號(hào)： | ISL8700A |
| 廠商： | Intersil Corporation |
| 英文描述： | Adjustable Quad Sequencer |
| 中文描述： | 可調(diào)四序 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 285K |
| 代理商： | ISL8700A |
4
FN6381.0
October 12, 2006
Functional Block Diagram
Functional Description
The ISL870XA family of ICs provides four delay adjustable
sequenced outputs while monitoring a single distributed voltage
in the nominal range of 3.3V to 24V for both under and
overvoltage. Only when the voltage is in compliance will the
ISL870XA initiate the pre-programmed A-B-C-D sequence of
the ENABLE (ISL8700A, ISL8702A, ISL8704A) or ENABLE#
(ISL8701A, ISL8703A, ISL8705A) outputs. Although this IC has
a bias range of 3.3V to 24V it can monitor any voltage >1.22V
via the external divider if a suitable bias voltage is otherwise
provided.
During initial bias voltage (V
IN
) application the ISL8700A,
ISL8702A, ISL8704A ENABLE outputs are held low once
V
IN
= 1V whereas the ISL8701A, ISL8703A, ISL8705A
ENABLE# outputs follow the rising V
IN
. Once V
IN
> the V bias
power on reset threshold (POR) of 2.8V, V
IN
is constantly
monitored for compliance via the input voltage resistor divider
and the voltages on the UV and OV pins and reported by the
FAULT output. Internally, voltage regulators generate 3.5V and
1.17V ±5% voltage rails for internal usage once V
IN
> POR.
Once UV > 1.22V and with the SEQ_EN pin high or open,
(SEQ_EN# must be pulled low on ISL8704A, ISL8705A) the
auto sequence of the four ENABLE (ENABLE#) outputs begins
as the TIME pin charges its external capacitor with a 2.6μA
current source. The voltage on TIME is compared to the
internal reference (V
TIME_VTH
) comparator input and when
greater than V
TIME_VTH
the ISL8700A, ISL8702A, ISL8704A
ENABLE_A is released to go high via an external pull-up
resistor or a pull-up in a DC/DC convertor enable input, for
example. Conversely, ENABLE#_A output will be pulled low at
this time on an ISL8701A, ISL8703A, ISL8705A. The time
delay generated by the external capacitor is to assure
continued voltage compliance within the programmed limits, as
during this time any OV or UV condition will halt the start-up
process. TIME cap is discharged once V
TIME_VTH
is met.
Once ENABLE_A is active (either released high on the
ISL8700A, ISL8702A, ISL8704A or pulled low, ISL8701A,
ISL8703A, ISL8705A) a counter is started and using the
resistor on TB as a timing component a delay is generated
before ENABLE_B is activated. At this time, the counter is
restarted using the resistor on TC as its timing component for
a separate timed delay until ENABLE_C is activated. This
process is repeated for the resistor on TD to complete the
A-B-C-D sequencing order of the ENABLE or ENABLE#
outputs. At any time during sequencing if an OV or UV event
is registered, all four ENABLE outputs will immediately return
to their reset state; low for ISL8700A, ISL8702A, ISL8704A
and high for ISL8701A, ISL8703A, ISL8705A. C
TIME
is
immediately discharged after initial ramp up thus waiting for
subsequent voltage compliance to restart. Once sequencing
is complete, any subsequently registered UV or OV event will
trigger an immediate and simultaneous reset of all ENABLE or
ENABLE# outputs.
VIN
VOLTAGE
REFERENCE
1.17V
INTERNAL VOLTAGE
REGULATOR
VIN (2.8V MIN - 27V MAX)
2.0V VIN POR
3.5V
LOGIC
VIN
PROGRAMMABLE
DELAY TIMER
V
TIME_VTH
2.6
μ
A
VIN
TB
TC
TD
ENABLE_A
ENABLE_B
ENABLE_C
ENABLE_D
TIME
GND
FAULT
SEQ_EN
UV
OV
+
-
-
+
eo
VREF
30
μ
s
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL8700AIBZ | Adjustable Quad Sequencer |
| ISL8701AIBZ | Adjustable Quad Sequencer |
| ISL8702AIBZ | Adjustable Quad Sequencer |
| ISL8703AIBZ | Adjustable Quad Sequencer |
| ISL8704AIBZ | Adjustable Quad Sequencer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL8700AIBZ | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL8700AIBZ-T | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL8700IBZ | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL8700IBZ-T | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL8701AIBZ | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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