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參數(shù)資料
| 型號： | ISL8724IRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Power Sequencing Controllers |
| 中文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-24 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 276K |
| 代理商： | ISL8724IRZ-T |
6
FN6413.0
December 21, 2006
the ~10ms enable delay to initiate DLY_ON cap charging
when released to go high. This feature can be used where
4 voltages can be monitored in addition to a on-off switch
position or, in the case of the ISL8724 a present pin pull
down.
Restart of the turn on sequence is automatic once all
requirements are met. This allows for no interaction
between the sequencer and a controller IC if so desired.
If no capacitors are connected between DLY_ON or
DLY_OFF pins and ground then all such related GATEs
start to turn on immediately after the 10ms (T
UVLOdel
)
ENABLE stabilization time out has expired and the GATEs
start to immediately turn off when ENABLE is deasserted.
Table 1 illustrates the nominal time delay from the start of
charging to the 1.27V reference for various capacitor
values on the DLY_X pins. This table does not include the
10ms of enable lock out delay during a start up sequence
but represents the time from the end of the enable lock out
delay to the start of GATE transition. There is no enable
lock out delay for a sequence off, so this table illustrates
the delay to GATE transition from a disable signal.
Figure 2 illustrates the turn-on and Figure 3 the nominal turnoff
timing diagrams of the
ISL8723
and
ISL8724
product.
Note the delay and flexible sequencing possibilities. Multiple
series, parallel or adjustable capacitors can be used to easily
fine tune timing between that offered by standard value
capacitors.
TABLE 1.
NOMINAL DELAY TO SEQUENCING THRESHOLD
DLY PIN CAPACITANCE
TIME (ms)
Open
0.02
100pF
0.135
1000pF
1.35
0.01
μ
F
13.5
0.1
μ
F
135
1
μ
F
1350
NOTE: Nom. T
DEL_SEQ
= dly_cap (μF) X 1.35M
Ω
ISL8723, ISL8724
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