fSCL SCL Frequency 400 kHz tIN
參數(shù)資料
型號： ISL95811WFRTZ-TK
廠商： Intersil
文件頁數(shù)： 10/14頁
文件大?。?/td> 0K
描述： IC POT 256TAPS 5BYTES 8-TDFN
標準包裝： 1,000
系列： XDCP™
接片： 256
電阻（歐姆）： 10k
電路數(shù)： 1
溫度系數(shù)： 標準值 ±45 ppm/°C
存儲器類型： 非易失
接口： I²C
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-WDFN 裸露焊盤
供應商設備封裝： 8-TDFN（3x3）
包裝： 帶卷 (TR)
5
FN6759.1
October 6, 2008
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STO:NV
STOP Condition Hold Time for Non-
Volatile Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
2s
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window.
0ns
tR (Note 16)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF (Note 16)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 16)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu (Note 16)
SDA and SCL Bus Pull-Up Resistor
Off-Chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2k
Ω~2.5kΩ.
For Cb = 40pF, max is about 15k
Ω~20kΩ
1k
Ω
tWC (Note 17)
Non-Volatile Write Cycle Time
12
20
ms
tSU:WP
WP Setup Time
Before START condition
600
ns
tHD:WP
WP Hold Time
After STOP condition
600
ns
NOTES:
4. Typical values are for TA = +25°C and 3.3V supply voltage.
5. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
6. ZS error = V(RW)0/LSB.
7. FS error = [V(RW)255 – VCC]/LSB.
8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 18)
TYP
(Note 4)
MAX
(Note 18) UNITS
ISL95811
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