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參數(shù)資料
| 型號： | ISL96017UIRT8Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 12/13頁 |
| 文件大小： | 0K |
| 描述： | IC XDCP 128-TAP 50KOHM 8-TDFN |
| 標準包裝： | 6,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 ±100 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
ISL96017
8
FN8243.2
June 8, 2012
Principles of Operation
This device combines a DCP, 16kbit non-volatile memory, and an
I2C serial interface providing direct communication between a
host and the DCP and memory.
DCP Description
The DCP has 10k
Ω or 50kΩ nominal total resistance and 128
taps. It is implemented with a combination of resistor elements
and CMOS switches. The physical ends of the DCP, the RH and RL
pins, are equivalent to the fixed terminals of a mechanical
potentiometer. The RW pin is connected to intermediate nodes,
and it is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP
is controlled by a 7-bit volatile DCP Register. When the DCP
Register contains all zeroes (00 hex, or “R0”), its wiper terminal,
RW, is closest to its RL terminal. When the DCP Register contains
all ones (7F hex, or “R127”), its wiper terminal is closest to its RH
terminal. As the value of the DCP Register increases from all
zeroes to all ones, the wiper moves monotonically from the
position closest to RL to the closest to RH. Therefore, the
resistance between RH and RW decreases monotonically from
R0 to R127, while the resistance between RW and RL increases
monotonically from R127 to R0.
While the device is being powered up, the DCP Register is reset
to 40 hex (64 decimal). Soon after the power supply voltage
becomes large enough for reliable non-volatile memory reading,
the device reads the value stored on the non-volatile Initial Value
Register (IVR) and loads it into the DCP Register.
Memory Description
This device contains 2048 non-volatile bytes organized in 128
pages of 16 bytes each. This allows writing 16 bytes on a single
I2C interface operation, followed by a single internal non-volatile
write cycle. The memory is accessed by I2C interface operations
with addresses 000 hex through 7FF hex.
Bytes at addresses 000 hex through 7FB hex are available to the
user as general purpose memory. The byte at address 7FF hex,
IVR, contains the initial value loaded at power-up into the volatile
DCP Register. The byte at address 7FE hex controls the access to
the DCP byte (See “Access to DCP Register and IVR”). Bytes at
addresses 7FC hex and 7FD hex, are reserved, which means that
they should not be written, and their value should be ignored if
they are read (see Table 1).
Access to DCP Register and IVR
The volatile DCP Register and the non-volatile (IVR) can be read
or written directly using the I2C serial interface, with Address
Byte 07FF hex.
The MSB of the byte at address 7FE hex is called “OnlyVolatile”
and controls the access to the DCP Register and IVR. This bit is
volatile and it’s reset to “0” at power up.
The Data Byte read from memory address 7FF hex, is from the
DCP register when the “OnlyVolatile” bit is “1”, and from the IVR
when this bit is “0”.
The Data Byte of a Write operation to memory address 7FF hex is
written only to the DCP Register when the “OnlyVolatile” bit is “1”,
and it’s written to both the DCP Register and the IVR when this
bit is “0”.
When writing to the “OnlyVolatile” bit at address 7FE hex, the
seven LSBs of the Data Byte must be all zeros.
Writing to address 7FE hex and 7FF hex can be done in two Write
operations, or one Write operation with two Data Bytes.
See next sections for interface protocol description.
TABLE 1. ISL96017 MEMORY MAP
ADDRESS
DATA BITS
FUNCTION
7FFh
0 D6 D5 D4 D3 D2 D1 D0
IVR, DCP
7FEh
OV 000
000
0
Access Control
7FDh
Reserved
7FCh
Reserved
7FBh
D7 D6 D5 D4 D3 D2 D1 D0 General Purpose Memory
000h
NOTE: OV = “Only Volatile”. All other bits in register 7FEh must be 0.
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