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參數(shù)資料
| 型號： | ISL96017UIRT8Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 0K |
| 描述： | IC XDCP 128-TAP 50KOHM 8-TDFN |
| 標準包裝： | 6,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 ±100 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
ISL96017
5
FN8243.2
June 8, 2012
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VDD to
SDA entering the 30% to 70% of VDD window
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VDD
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL falling edge. Both
crossing 70% of VDD
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20+
0.1*Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20+
0.1*Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-Up Resistor Off-Chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2~2.5k
Ω
For Cb = 40pF, max is about 15~20k
Ω
1
k
Ω
tSU:WP
WP Setup Time
Before START condition
600
ns
tHD:WP
WP Hold Time
After STOP condition
600
ns
NOTES:
5. Typical values are for TA = 25°C and VDD = 3.3V.
6. LSB = (V(RW)127 – V(RW)0)/127. V(RW)127 and V(RW)0 are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively.
7. FSerror = (V(RW)127 – VDD)/LSB
8. ZSerror = V(RW)0/LSB
9. DNL = [(V(RW) i – V(RW) i-1)/LSB] – 1, for i from 1 to 127. i is the DCP Register setting.
10. INL = [V(RW) i – i * LSB – V(RW)0]/LSB, for I = 1 to 127.
11.
for i = 16 to 111, and T = -40°C to 85°C
12. MI = (R0 – R127)/127. MI is minimum increment. R0 and R127 are the resistances between RH and RW with the DCP Register set to 00 hex and 7F
hex, respectively.
13. RDNL = (R i – R i-1)/MI – 1, for i from 1 to 111. i is the DCP Register setting.
14. RINL = [R i – (MI * i) – R127]/MI, for i from 1 to 111.
15.
; for i = 1 to 111, and T = -40°C to 85°C
16. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid
STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
17. Parameter is not 100% tested.
18. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 18)
TYP
(Note 5)
MAX
(Note 18)
UNIT
TC
V
Max V RW
()i
() Min V RW
()i
()
–
[]
Max V RW
()i
() Min V RW
()i
()
+
() 2
-----------------------------------------------------------------------------------------------
10
6
125
°C
-----------------
×
=
TC
R
Max Ri
() Min Ri
()
–
[]
Max Ri
() Min Ri
()
+
[] 2
----------------------------------------------------------------
110
6
×
125
°C
-------------------
×
=
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