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參數(shù)資料
| 型號： | ISL96017WIRT8Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP 128-TAP 10KOHM 8-TDFN |
| 標準包裝： | 6,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 ±100 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
ISL96017
9
FN8243.2
June 8, 2012
I2C Serial Interface
This device supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, this device operates as a slave device in all
applications. All communication over the I2C interface is
conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (See Figure 7). On power
up, the SDA pin is in the input mode. All I2C interface operations
must begin with a START condition, which is a HIGH to LOW
transition of SDA while SCL is HIGH. The device continuously
monitors the SDA and SCL lines for the START condition and does
not respond to any command until this condition is met (See
Figure 7). A START condition is ignored during the power up
sequence and during internal non-volatile write cycles. All I2C
interface operations must be terminated by a STOP condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH (See
Figure 7). A STOP condition at the end of a Read operation, or at
the end of a Write operation to volatile bytes only places the
device in its standby mode. A STOP condition during a Write
operation to a non-volatile byte, initiates an internal non-volatile
write cycle. The device enters its standby state when the internal
non-volatile write cycle is completed.
An ACK, Acknowledge, is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (See
Figure 8). This device responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and once
again after successful receipt of the Address Byte. This device
also responds with an ACK after receiving each Data Byte of a
Write operation. The master must respond with an ACK after
receiving each Data Byte of a read operation except the last one.
A valid Identification Byte contains 1010 as the four MSBs. The
following three bits are the MSBs of the memory address to be
accessed. The LSB of the Identification Byte is the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation (see Table 2). The complete memory address location
to be accessed is a 11-bit word, since the memory has 2048
bytes. The eight LSBs are in the Address Byte.
TABLE 2. IDENTIFICATION BYTE FORMAT
10
1
0
A10
A9
A8
R/Wb
MSB
LSB
SCL
SDA
START
STOP
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 7. VALID DATA CHANGES, START AND STOP CONDITIONS
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