4 FN8243.2 June 8, 2012 TCV (Note 11, 17) Ratiometric Temperature Coefficient DCP Regis" />
參數(shù)資料
型號: ISL96017WIRT8Z-T
廠商: Intersil
文件頁數(shù): 8/13頁
文件大?。?/td> 0K
描述: IC XDCP 128-TAP 10KOHM 8-TDFN
標(biāo)準(zhǔn)包裝: 6,000
接片: 128
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±100 ppm/°C
存儲器類型: 非易失
接口: I²C
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN(3x3)
包裝: 帶卷 (TR)
ISL96017
4
FN8243.2
June 8, 2012
TCV
(Note 11, 17)
Ratiometric Temperature
Coefficient
DCP Register between 10 hex and 6F hex
±4
ppm/°C
DNL (Note 6, 9) Differential Non-Linearity
Monotonic over all tap positions
-0.75
0.75
LSB
INL (Note 6, 10) Integral Non-Linearity
-1
1
LSB
DCP IN RESISTOR MODE (Measurements between RH and RW with RL not connected)
R127 (Note 12) Resistance Offset.
U version - DCP Register set to 7F hex.
Measured between RH and RW pins.
0
0.5
2
MI
W version - DCP Register set to 7F hex.
Measured between RH and RW pins.
1
5
MI
TCR
(Note 15,17)
Resistance Temperature Coefficient
±100
ppm/°C
RDNL
(Note 12,13)
Resistance Differential Non-Linearity
-0.75
0.75
MI
(Note 1)
RINL
(Note 12,14)
Resistance Integral Non-Linearity
-1
1
MI
(Note 1)
EEPROM SPECS
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
At 55°C
50
Years
tWC (Note 16) Non-Volatile Write Cycle Time
6
12
ms
SERIAL INTERFACE SPECS
VIL
WP, SDA, and SCL Input Buffer LOW Voltage
-0.3
0.3*
VDD
V
VIH
WP, SDA and SCL Input Buffer HIGH Voltage
0.7*
VDD
+0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*
VDD
V
VOL
SDA Output Buffer LOW Voltage, Sinking
4mA
00.4
V
Cpin
WP, SDA, and SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at SDA and
SCL Inputs.
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data Valid
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
900
ns
tBUF
Time the Bus Must be Free Before the Start of
a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VDD to
SCL falling edge crossing 70% of VDD
600
ns
Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 18)
TYP
(Note 5)
MAX
(Note 18)
UNIT
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