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參數(shù)資料
| 型號(hào)： | ISL97522 |
| 廠(chǎng)商： | Intersil Corporation |
| 英文描述： | 4-Channel TFT-LCD Supply |
| 中文描述： | 4通道的TFT - LCD電源 |
| 文件頁(yè)數(shù)： | 18/20頁(yè) |
| 文件大?。?/td> | 418K |
| 代理商： | ISL97522 |
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18
FN7445.0
December 13, 2006
Fault Protection
During the startup sequence, prior to BOOST soft-start,
V
REF
is checked to be within ±20% of its final value and the
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
If C
DELAY
is shorted low, then the sequence will not start,
while if C
DELAY
is shorted H, the first down ramp will not
occur and the sequence will not complete.
Once the start-up sequence is completed, the chip
continuously monitors C
DLY
, DELB, FBP, FBL, FBN, V
REF
and FBB for faults. During this time, the voltage on the C
DLY
capacitor remains at 1.15V until either a fault is detected, or
the EN pin is pulled low.
A fault on C
DELAY
, V
REF
or temperature will shut down the
chip immediately. If a fault on any other output is detected,
C
DELAY
will ramp up linearly with a 5μA (typical) current to
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C
DLY
capacitor returns to 1.15V.
Typical fault thresholds for FBP, FBL, FBN and FBB are
included in the tables. DELB fault threshold is typically 0.6V.
C
INTB
and C
INTL
have an internal current-limited clamp to
keep the voltage within their normal ranges. If they are
shorted low, the regulators will attempt to regulate to 0V.
If any of the regulated outputs (AVDD, V
ON
, V
OFF
or
V
LOGIC
) are driven above their target levels the drive
circuitry will switch off until the output returns to its expected
value.
If AVDD and V
LOGIC
are excessively loaded, the current
limit will prevent damage to the chip. While in current limit,
the part acts like a current source and the regulated output
will drop. If the output drops below the fault threshold, a
ramp will be initiated on C
DELAY
and, provided that the fault
is sustained, the chip will be disabled on completion of the
ramp.
In some circumstances, (depending on ambient temperature
and thermal design of the board), continuous operation at
current limit may result in the over-temperature threshold
being exceeded, which will cause the part to disable
immediately.
All I/O also have ESD protection, which in many cases will
also provide overvoltage protection, relative to either ground
or V
DD
. However, these will not generally operate unless
abs max ratings are exceeded.
Component Selection for Start-Up Sequencing and
Fault Protection
The C
REF
capacitor is typically set at 220nF and is required
to stabilize the V
REF
output. The range of C
REF
is from
22nF to 1μF and should not be more than five times the
capacitor on C
DEL
to ensure correct start-up operation.
The C
DEL
capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching μA levels.
C
DEL
should be at least 1/5 of the value of C
REF
(See
above). Note with 220nF on C
DEL
the fault time-out will be
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1μF will give a fault time-out
period of typically 230ms).
Fault Sequencing
The ISL97522 has an advanced fault detection system
which protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of 140°C, the device will shut
down.
Layout Recommendation
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place V
REF
, V
DC
and V
DCP
bypass capacitors close to
the pins.
3. Minimize the length of traces carrying fast signals and
high current.
4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
ISL97522
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