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參數(shù)資料
| 型號： | ISL97522IRZ-TK |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 4-Channel TFT-LCD Supply |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, QCC38 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-220, QFN-38 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 418K |
| 代理商： | ISL97522IRZ-TK |
16
FN7445.0
December 13, 2006
Buck Inductor
An inductor value in the range 3.3-10μH is recommended for
the buck converter. Besides the inductance, the DC
resistance and the saturation current should also be
considered when choosing buck inductor. Low DC
resistance can help maintain high efficiency, and the
saturation current rating should be at least maximum output
current plus half of ripple current.
Buck MOSFET
The principle to select Buck MOSFET is similar to that of
Boost. The voltage of stress of buck converter should be
maximum input voltage plus reasonable margin, and the
current rating should be over the maximum output current.
The r
DS(ON)
of this MOSFET should be in the range from
20m
Ω
to 50m
Ω
.
Rectifier Diode (Buck Converter)
A Schottky diode is recommended due to fast recovery and
low forward voltage. The reverse voltage rating should be
higher than the maximum input voltage. The average current
should be as the following equation,
Where I
O
is the output current of buck converter.
Output Capacitor (Buck Converter)
Four 10μF or two 22μF ceramic capacitors are
recommended for this part. The overshoot and undershoot
will be reduced with more capacitance, but the recovery time
will be longer.
PI Loop Compensation (Buck Converter)
The buck converter of ISL97522 can be compensated by a
RC network connected from CINTL pin to ground. C27 =
4.7nF and R17= 2k RC network is used in the demo board.
The larger value resistor can lower the transient overshoot,
however, at the expense of stability of the loop.
The stability can be optimized in a similar manner to that
described in the section on "PI Loop Compensation (Boost
Converter)”.
Bootstrap Capacitor (C28)
This capacitor is used to provide the supply to the high driver
circuitry for the buck MOSFET. The bootstrap supply is
formed by an internal diode and capacitor combination. A
1μF is recommended for ISL97522. A low value capacitor
can lead to overcharging and in turn damage the part.
If the load is too light, the on-time of the low side diode may
be insufficient to replenish the bootstrap capacitor voltage. In
this case, if V
IN
-V
BUCK
< 1.5V, the internal MOSFET pull-up
device may be unable to turn-on until V
LOGIC
falls. Hence,
there is a minimum load requirement in this case. The
minimum load can be adjusted by the feedback resistors
to FBL.
The bootstrap capacitor can only be charged when the
higher side MOSFET is off. If the load is too light which can
not make the on time of the low side diode be sufficient to
replenish the boot strap capacitor, the MOSFET can’t turn
on. Hence there is minimum load requirement to charge the
bootstrap capacitor properly.
Start-Up Sequence
Figure 21 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at V
CDLY
.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
If EN is L, the device is powered down. If EN is H, and the
input voltage (V
IN
) exceeds 2.5V, an internal current source
starts to charge C
DLY
to an upper threshold using a fast
ramp followed by a slow ramp. If EN is low at this point, the
C
DLY
ramp will be delayed until EN goes high.
The first four ramps on C
DLY
(two up, two down) are used to
initialize the fault protection switch and to check whether
there is a fault condition on C
DLY
or V
REF
. If a fault is
detected, the outputs and the input protection will turn off
and the chip will power down.
If no fault is found, C
CDLY
continues ramping up and down
until the sequence is completed.
During the second ramp, the device checks the status of
V
REF
and over temperature.
Initially the boost is not enabled so V
BOOST
rises to V
IN
-
V
DIODE
through the output diode. Hence, there is a step at
V
BOOST
during this part of the start-up sequence. If this step
is not desirable, an external PMOS FET can be used to delay
the output until the boost is enabled internally. The delayed
output appears at A
VDD
.
V
BOOST
soft-starts at the beginning of the third ramp. The
soft-start ramp depends on the value of the C
DLY
capacitor.
For C
DLY
of 220nF, the soft-start time is ~2ms.
V
OFF
turns on at the start of the fourth peak. At the fifth
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q3 to generate a delayed V
BOOST
output.
V
ON
is enabled at the beginning of the sixth ramp. A
VDD
,
V
OFF
, DELB and V
ON
are checked at end of this ramp.
Vlogic’s start-up is controlled by ENL. When ENL is L, Vlogic
is off, and when ENL is H, V
LOGIC
is on.
I
AVG
1
D
–
(
)
*I
O
=
(EQ. 19)
ISL97522
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