參數(shù)資料
型號: ISP1160BD-S
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 41/88頁
文件大?。?/td> 394K
代理商: ISP1160BD-S
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
46 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.2.3
HcFmNumber register (R: 0FH)
The HcFmNumber register is a 16-bit counter. It provides a timing reference for
events happening in the HC and the HCD. The HCD may use the 16-bit value
specied in this register and generate a 32-bit frame number without requiring
frequent access to the register.
Code (Hex): 0F — read
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FR[13:8]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
FR[7:0]
Reset
00000000
Access
RRRRRRRR
Table 23:
HcFmRemaining register: bit description
Bit
Symbol
Description
31
FRT
FrameRemainingToggle: This bit is loaded from the
FrameIntervalToggle eld of the HcFmInterval register whenever
FrameRemaining reaches 0. This bit is used by the HCD for
synchronization between FrameInterval and FrameRemaining.
30 to 14
-
reserved
13 to 0
FR[13:0]
FrameRemaining: This counter is decremented at each bit time.
When it reaches zero, it is reset by loading the FrameInterval value
specied in the HcFmInterval register at the next bit time boundary.
When entering the USBOperational state, the HC reloads it with
the content of the FrameInterval part of the HcFmInterval register
and uses the updated value from the next SOF.
Table 24:
HcFmNumber register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
FN[15:8]
Reset
00000000
Access
RRRRRRRR
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