參數(shù)資料
型號(hào): ISP1160BD-S
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 54/88頁(yè)
文件大?。?/td> 394K
代理商: ISP1160BD-S
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
58 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.4.2
HcDMAConguration register (R/W: 21H/A1H)
Code (Hex): 21 — read
Code (Hex): A1 — write
2
InterruptOutputPolarity
0 — active LOW
1 — active HIGH
1
InterruptPinTrigger
0 — interrupt is level-triggered
1 — interrupt is edge-triggered
0
InterruptPinEnable
This bit is used as pin INT’s master interrupt enable and
should be used together with register
Hc
PInterruptEnable to enable pin INT.
0 — pin INT is disabled
1 — pin INT is enabled
Table 37:
HcHardwareConguration register: bit description…continued
Bit
Symbol
Description
Table 38:
HcDMAConguration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
BurstLen[1:0]
DMA
Enable
reserved
DMA
Counter
Select
ITL_ATL_
DataSelect
DMARead
WriteSelect
Reset
00000000
Access
R/W
Table 39:
HcDMAConguration register: bit description
Bit
Symbol
Description
15 to 7
-
reserved
6 to 5
BurstLen[1:0]
00 — single-cycle burst DMA
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
4
DMAEnable
0 — DMA is terminated
1 — DMA is enabled
This bit will be reset to logic 0 when DMA transfer is completed.
3
-
reserved
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