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| 型號(hào)： | ISP1161 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | 全速通用串行總線的單芯片主機(jī)和設(shè)備控制器 |
| 文件頁(yè)數(shù)： | 34/127頁(yè) |
| 文件大小： | 2762K |
| 代理商： | ISP1161 |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
34 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
One interrupt is issued concurrently with the SOF. This interrupt (the ITLint is set in
the Hc
μ
PInterrupt register) triggers reading and writing of the ITL by the
microprocessor, after which the interrupt is cleared by the microprocessor.
Next the programmable AT Interrupt (the ATLint is set in the Hc
μ
PInterrupt Register)
is issued, which triggers reading and writing of the ITL by the microprocessor, after
which the interrupt is cleared by the microprocessor. If the microprocessor cannot
handle the ISO interrupt before the next ISO interrupt, disrupted ISO traffic can result.
To be able to send more than one packet to the same Control or Bulk endpoint in the
same frame, an active bit and a ’TotalBytes of transfer’ field are introduced (see
Table 5
). The active bit is cleared only if all data of the Philips Transfer Descriptor
(PTD) are transferred or if a transaction at that endpoint contained a fatal error. If all
PTD of the ATL are serviced once and the frame is not over yet, the HC starts looking
for a PTD with the active bit still set. If such a PTD is found and there is still enough
time in this frame, another transaction is started on the USB bus for this endpoint.
For ISO processing, the Host Controller Driver has also to take care of the
BufferStatus register (2CH, Read only) for the ITL buffer RAM operations. After the
Host Controller Driver writes ISO data into ITL buffer RAM, the ITL0BufferFull or
ITL1BufferFull bit (depends if it is ITL0 or ITL1) will be set to logic 1.
After the HC processes the ISO data in the ITL buffer RAM then the corresponding
ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.
The Host Controller Driver can clear the buffer status bits by a read of the ITL buffer
RAM, and this must be done within the 1 ms frame from which the ITL0BufferDone or
ITL1BufferDone was set. Failure to do so will cause the ISO processing to stop and a
power on reset or software reset will have to be applied to the HC, a USB reset to the
USB bus must
not
be made.
For example, in the first frame, for the HCD doing a write of ISO-A data into the ITL0
buffer. This will cause the BufferStatus register to show that the ITL0 buffer is full by
setting the ITL0BufferFull bit to logic 1. At this stage the Host Controller Driver cannot
write ISO data into the ITL0 buffer RAM again.
In the second frame, the Host Controller will process the ISO-A data in the ITL0
buffer. At the same time, the HCD can write ISO-B data into ITL1 buffer. When the
next SOF comes (the beginning of the third frame), both the ITL1BufferFull and
ITL0BufferDone are automatically set to logic 1. In the third frame the HCD has to
read ITL0 buffer at least two bytes (one word) to clear
both
the ITL0BufferFull and
ITL0BufferDone bits. If both are not cleared, when the next SOF comes (the
beginning of the fourth frame) the ITL0BufferDone bit will be cleared automatically,
but the ITL0BufferFull bit remains at logic 1 and the ITL0BufferFull bit will be unable
to be cleared. This condition will disable the HCD from writing ISO data into the ITL0
buffer again and ISO processing be unable to be carried on. This also applies to the
ITL1 buffer because the ITL0 and ITL1 are Ping-Pong structured buffers. To recover
from this state the power on reset or software reset will have to be applied on the HC.
Time domain behavior
In the first example the CPU is fast enough to read back and download a scenario
before the next interrupt. Note that on the ISO interrupt of frame N:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1161A1 | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BM | Universal Serial Bus single-chip host and device controller |
| ISP1161BD | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1161A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161A1BD,118 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BD,151 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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