參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 71/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
71 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.5.2
HcScratch register (R/W: 28H/A8H)
This register is for the HCD to save and restore values when required.
Code (Hex): 28 —
read
Code (Hex): A8 —
write
10.5.3
HcSoftwareReset register (W: A9H)
This register provides a means for software reset of the HC. To reset the HC, the HCD
must write a reset value of F6H to this register. Upon receiving the reset value, the
HC resets all the registers except its buffer memory.
Code (Hex): A9 —
write
Table 48:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcScratch register: bit allocation
15
14
13
12
11
10
9
8
Scratch[15:8]
0
R/W
4
Scratch[7:0]
0
R/W
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 49:
Bit
15 to 0
HcScratch register: bit description
Symbol
Description
Scratch[15:0]
Scratch register value
Table 50:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcSoftwareReset register: bit allocation
15
14
13
12
11
10
9
8
Reset[15:8]
0
W
7
0
W
6
0
W
5
0
W
4
0
W
3
0
W
2
0
W
1
0
W
0
Reset[7:0]
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Table 51:
Bit
15 to 0
HcSoftwareReset register: bit description
Symbol
Description
Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the
registers except its buffer memory.
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ISP1161 Full-speed Universal Serial Bus single-chip host and device controller
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