參數(shù)資料
型號: ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁數(shù): 53/87頁
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
53 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Task File register 1F7 is a write-only register; a read will return FFh.
9.4.6
DMA Interrupt Reason register (address: 50h)
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after
a DMA command has been executed. An interrupt source is cleared by writing logic 1
to the corresponding bit. When reading, AND the value of the bits in this register with
the value of the corresponding bits in the DMA Interrupt Enable register.
The bit allocation is given in
Table 70
.
Table 66:
CS1_N = H, CS0_N = L, DA2 = H, DA1 = H, DA0 = L.
Bit
7
Symbol
Reset
0
Bus reset
0
Access
R/W
Task File 1F6 register (address: 4Dh): bit allocation
6
5
4
3
2
1
0
drive/head/LBA[27:24] (ATA) or drive (ATAPI)
0
0
0
0
R/W
R/W
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 67:
CS1_N = H, CS0_N = L, DA2 = H, DA1 = H, DA0 = H.
Bit
7
Symbol
Reset
0
Bus reset
0
Access
W
Task File 1F7 register (address: 44h): bit allocation
6
5
4
3
2
1
0
command (ATA) or status
[1]
/command (ATAPI)
0
0
0
0
W
W
0
0
W
0
0
W
0
0
W
0
0
W
0
0
W
Table 68:
CS1_N = L, CS0_N = H, DA2 = H, DA1 = H, DA0 = L.
Bit
7
Symbol
Reset
0
Bus reset
0
Access
R/W
Task File 3F6 register (address: 4Eh): bit allocation
6
5
4
3
2
1
0
alternate status/command (ATA or ATAPI)
0
0
0
0
R/W
R/W
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 69:
CS1_N = L, CS0_N = H, DA2 = H, DA1 = H, DA0 = H.
Bit
7
Symbol
Reset
0
Bus reset
0
Access
R/W
Task File 3F7 register (address: 4Fh): bit allocation
6
5
4
3
2
1
0
drive address (ATA) or reserved (ATAPI)
0
0
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
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