參數(shù)資料
型號(hào): ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 1/158頁
文件大?。?/td> 724K
代理商: ISP1761
1.
General description
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with the advanced Philips Slave Host Controller and the Philips
ISP1582 Peripheral Controller.
The Hi-Speed USB Host Controller and Peripheral Controller comply to Universal Serial
Bus Specification Rev. 2.0and support data transfer speeds of up to 480 Mbit/s. The
Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is
adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus
Rev. 1.0 The OTG controller is compliant with On-The-Go Supplement to the USB
Specification Rev. 1.0a
The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always configured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as specified in the OTG supplement.
2.
Features
I
Compliant with Universal Serial Bus Specification Rev. 2.0 supporting data transfer at
high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
I
Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)
peripheral support
I
Three USB ports that support three operational modes:
N
Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller
ports
N
Mode 2: Ports 1, 2 and 3 are Host Controller ports
N
Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller
ports
I
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
I
Multitasking support with Virtual Segmentation feature (up to four banks)
I
High-speed memory controller (variable latency and SRAM external interface)
I
Directly addressable memory architecture
I
Generic processor interface to most CPUs, such as: Hitachi
SH-3 and SH-4, Philips
XA, Intel
StrongARM
, NEC
and Toshiba
MIPS, Motorola
DragonBall and
PowerPC
Reduced Instruction Set Computer (RISC) processors
I
Configurable 32-bit and 16-bit external memory data bus
I
Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
I
Slave DMA implementation on CPU interface for reducing the host system’s CPU load
ISP1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 01 — 12 January 2005
Product data sheet
相關(guān)PDF資料
PDF描述
ISP1761BE Hi-Speed Universal Serial Bus On-The-Go controller
ISP1761ET Hi-Speed Universal Serial Bus On-The-Go controller
ISP2100A Telecommunication IC
ISP2100BN4 Microprocessor
ISP2300 Controller Miscellaneous - Datasheet Reference
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ISP1761BE,518 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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