參數(shù)資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 6/164頁
文件大?。?/td> 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
102 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.3 Clear buffer
Use clear buffer when data needs to be discarded under the following conditions:
IN endpoint: If the host aborts a read operation, the residual data in the IN endpoint
buffer must be cleared using the Clear Buffer command. See Table 126.
OUT endpoint: If the host aborts a write operation, the residual data in the OUT
endpoint buffer must be cleared using the CLBUF bit. See Table 113.
For example, to clear a double buffer data IN endpoint 1, set the following registers in the
rmware as:
1. Assign a value to the Endpoint Index register. It can be any value other than the value
assigned to the DMA Endpoint register. In this example, do not assign 3h to the
Endpoint Index register. See remark in Section 10.6.1.
2. Assign DMA Endpoint register = 3h
3. Assign DMA Command register = 0Fh
4. Assign DMA Endpoint register = 3h
5. Assign DMA Command register = 0Fh
For example, to clear a double buffer data OUT endpoint 1, set the following registers in
the rmware as:
1. Assign a value to the DMA Endpoint register. It can be any value other than the value
assigned to the Endpoint Index register. In this example, do not assign 2h to the DMA
Endpoint register. See remark in Section 10.6.1.
2. Assign Endpoint Index register = 2h
3. Assign Control Function register = 10Fh
4. Assign Endpoint Index register = 2h
5. Assign Control Function register = 10Fh
10.4 Differences between the ISP1761 and ISP1582 peripheral controllers
This section explains the variations between the ISP1761 and ISP1582 peripheral
controllers in terms of register bits and their associated functions.
10.4.1 ISP1761 initialization registers
The ISP1582 supports 16-bit bus access. The register addresses are 2 bytes aligned.
The ISP1761 supports 16-bit and 32-bit bus accesses. To support the 32-bit access,
the DATA_BUS_WIDTH bit in the HW Mode Control register must be initialized.
EP6TX
programmable
yes
programmable
IN
EP7RX
programmable
yes
programmable
OUT
EP7TX
programmable
yes
programmable
IN
Table 96.
Endpoint access and programmability …continued
Endpoint
identier
Maximum packet
size
Double buffering Endpoint type
Direction
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