參數(shù)資料
型號: ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 36/158頁
文件大?。?/td> 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
36 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
8.2.3
USBINTR register (R/W: 0028h)
All the bits in this register are reserved.
8.2.4
FRINDEX register (R/W: 002Ch)
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125
μ
s (once each microframe). Bits n to 3
are used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in the FLS (Frame List Size) field of the USBCMD register.
This register must be written as a Double Word. A Word-only write (16-bit mode) produces
undefined results. This register cannot be written unless the Host Controller is in the
halted state as indicated by the HCH (HCHalted) bit. A write to this register while the RS
(Run/Stop) bit is set produces undefined results. Writes to this register also affect the SOF
value. The bit allocation is given in
Table 19
.
Table 17:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
USBSTS register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
1
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
FLR
0
R/W
R/W
2
PCD
0
R/W
R/W
1
R/W
0
reserved
[1]
reserved
[1]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 18:
Bit
31 to 4
3
USBSTS register: bit description
Symbol Description
[1]
-
reserved; write logic 0
FLR
Frame List Rollover
: The Host Controller sets this bit to logic 1 when the
Frame List Index rolls over from its maximum value to zero.
PCD
Port Change Detect
: The Host Controller sets this bit to logic 1 when any
port, where the PO bit is cleared, has a change to a one or a FPR bit
changes to a one as a result of a J-K transition detected on a suspended
port.
-
reserved
2
1 to 0
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