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參數(shù)資料
| 型號(hào)： | ISPLSI 1016-90LT44 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 32I/O 12NS 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | ispLSI® 1000 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 12.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 門數(shù)： | 2000 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI1016-90LT44 |
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Specifications ispLSI 1016
13
Input – Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load
programming data into the device. SDI/IN 0 also is
used as one of the two control pins for the isp state
machine.
Input – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as a pin to control the
operation of the isp state machine.
Input/Output – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an output pin to read
serial shift register data.
Input – This pin performs two functions. It is a
dedicated clock input when ispEN is logic high. This
clock input is brought into the Clock Distribution
Network, and can optionally be routed to any GLB
and/or I/O cell on the device. When ispEN is logic low,
it functions as a clock pin for the Serial Shift Register.
Dedicated Clock input. This clock input is connected
to one of the clock inputs of all of the GLBs on the
device.
This pin performs two functions:
– Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can
optionally be routed to any GLBand/or I/O
cellon the device.
– Active Low (0) Reset pin which resets all of the
GLB and I/O registersin the device.
1. Pins have dual function capability.
GND
1,
23
17, 39
1,
23
VCC
12, 34
6,
28
12, 34
Input/Output Pins - These are the general purpose I/O
pins used by the logic array.
Dedicated input pins to the device.
IN 3
2
40
2
I/O 0 - I/O 3
15, 16, 17, 18, 9,
10, 11, 12, 15, 16, 17, 18,
I/O 4 - I/O 7
19, 20, 21, 22, 13, 14, 15, 16, 19, 20, 21, 22,
I/O 8 - I/O 11
25, 26, 27, 28, 19, 20, 21, 22, 25, 26, 27, 28,
I/O 12 - I/O 15
29, 30, 31, 32, 23, 24, 25, 26, 29, 30, 31, 32,
I/O 16 - I/O 19
37, 38, 39, 40, 31, 32, 33, 34, 37, 38, 39, 40,
I/O 20 - I/O 23
41, 42, 43, 44, 35, 36, 37, 38, 41, 42, 43, 44,
I/O 24 - I/O 27
3,
4,
5,
6,
41, 42, 43, 44, 3,
4,
5,
6,
I/O 28 - I/O 31
7,
8,
9,
10 1,
2,
3,
4
7,
8,
9,
10
Table 2 - 0002C-16-isp
Ground (GND)
V
CC
ispEN
13
7
13
SDI/IN 0 1
14
8
14
MODE/IN 2 1
36
30
36
SDO/IN 1 1
24
18
24
SCLK/Y2 1
33
27
33
Y0
11
5
11
Y1/RESET
35
29
35
PLCC
PIN NUMBERS
TQFP
PIN NUMBERS
JLCC
PIN NUMBERS
DESCRIPTION
NAME
Pin Description
ALL
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI1016-90LT44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1016E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E_02 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E_06 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E100LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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