Specifications ispLSI 1032 6 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data she" />
參數(shù)資料
型號(hào): ISPLSI 1032-90LT
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 15/17頁
文件大?。?/td> 0K
描述: IC PLD ISP 64I/O 12NS 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispLSI® 1000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 12.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 32
門數(shù): 6000
輸入/輸出數(shù): 64
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: ISPLSI1032-90LT
Specifications ispLSI 1032
6
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Internal Timing Parameters1
ns
7.3
1.3
1.3
6.0
4.6
2.7
4.0
4.0
3.3
5.3
2.0
2.7
4.0
5.0
6.0
10.6
8.6
9.3
10.6
12.7
1.3
2.7
3.3
13.3
12.0
9.9
3.3
0.7
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-60
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
tgrp32
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
ORP
torp
torpbp
#
2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 32 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
5.5
1.0
1.0
4.5
3.5
2.0
3.0
3.0
2.5
4.0
1.5
2.0
3.0
3.8
4.5
8.0
6.5
7.0
8.0
9.5
1.0
2.0
2.5
10.0
9.0
7.5
2.5
0.5
MIN. MAX.
-80
4.8
2.1
1.2
3.6
2.8
1.6
2.4
2.4
2.8
3.2
1.2
1.6
2.4
3.0
3.6
6.4
5.2
5.7
7.0
8.2
0.8
1.6
2.0
8.0
7.8
6.0
2.4
0.4
MIN. MAX.
-90
ALL
DEVICES
DISCONTINUED
相關(guān)PDF資料
PDF描述
ISPLSI 1032E-125LJN IC PLD ISP 64I/O 7.5NS 84PLCC
ISPLSI 1032EA-200LT100 IC PLD ISP 64I/O 4.5NS 100TQFP
ISPLSI 1048-50LQI IC PLD ISP 96I/O 18NS 120PQFP
ISPLSI 1048C-50LQI IC PLD ISP 96I/O 22NS 128PQFP
ISPLSI 1048E-125LTN IC PLD ISP 96I/O 7.5NS 128TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI1032-90LT 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1032-90LT/833 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1032-90LTI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1032E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1032E_06 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD