Specifications ispLSI 1032 9 Maximum GRP Delay vs GLB Loads ispLSI 1032-80 ispLSI 1032-60 ispLSI 1032-90 0126A-80-32-isp 1 2 3 4 8 12 16 GLB Lo" />
參數(shù)資料
型號: ISPLSI 1032-90LT
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 2/17頁
文件大小: 0K
描述: IC PLD ISP 64I/O 12NS 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispLSI® 1000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 12.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 32
門數(shù): 6000
輸入/輸出數(shù): 64
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: ISPLSI1032-90LT
Specifications ispLSI 1032
9
Maximum GRP Delay vs GLB Loads
ispLSI 1032-80
ispLSI 1032-60
ispLSI 1032-90
0126A-80-32-isp
1
2
3
4
8
12
16
GLB Loads
GRP
Delay
(ns)
4
5
6
0
Power Consumption
ure 3 shows the relationship between power and operat-
ing speed.
Power consumption in the ispLSI 1032 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
50
100
150
200
250
0
1020
3040
50
60
70
fmax (MHz)
I CC
(mA)
80
Notes: Configuration of eight 16-bit Counters
Typical Current at 5V, 25C
ispLSI 1032
0127A-32-80-isp
ICC can be estimated for the ispLSI 1032 using the following equation:
ICC = 52 + (# of PTs * 0.30) + (# of nets * Max. freq * 0.009) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
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