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參數(shù)資料
| 型號： | ISPLSI 1048EA-170LQ128 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 96I/O 5NS 128PQFP |
| 標準包裝： | 24 |
| 系列： | ispLSI® 1000EA |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 5.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 48 |
| 門數(shù)： | 8000 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BQFP |
| 供應商設備封裝： | 128-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI1048EA-170LQ128 |
Specifications ispLSI 1048EA
10
USE
ispMA
CH
4A5
FOR
NEW
5V
DESIGNS
0127/1048EA
Icc can be estimated for the ispLSI 1048EA using the following equation:
Icc = 20mA + (# of PTs * .45) + (# of nets * Max Freq * .0087)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
fmax (MHz)
Notes: Configuration of twelve 16-bit counters, Typical current at 5V, 25C
400
300
200
100
0
25
50
75
100
125
150
175
I CC
(mA)
ispLSI 1048EA
500
Power Consumption
Power consumption in the ispLSI 1048EA device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
Package Thermal Characteristics
For the ispLSI 1048EA-170, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (TJ) with power supplied is not
exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-
mum allowable junction temperature (TJ) specification.
Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for addi-
tional information on calculating TJ.
Maximum GRP Delay vs. GLB Loads
GLB Load
3
1
8
16
32
48
GRP
Delay
(ns)
4
5
4
2
GRP/GLB/1048EA
1
ispLSI 1048EA-170
ispLSI 1048EA-125
ispLSI 1048EA-100
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1048EA-170LQ128 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1048EA-170LT128 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2030A-110LJ44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| ISPLSI2030A-110LT44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| ISPLSI2030A-110LT48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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