Specifications ispLSI 2096/A 9 USE ispLSI 2096E FOR NEW DESIGNS Pin Description Input - This pin performs two functions. When ispEN is logic lo" />
參數(shù)資料
型號(hào): ISPLSI 2096A-100LTN128
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 12/12頁(yè)
文件大?。?/td> 0K
描述: IC PLD ISP 96I/O 10NS 128TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispLSI® 2000A
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 24
宏單元數(shù): 96
門(mén)數(shù): 4000
輸入/輸出數(shù): 96
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x14)
包裝: 托盤(pán)
其它名稱: ISPLSI2096A-100LTN128
Specifications ispLSI 2096/A
9
USE
ispLSI
2096E
FOR
NEW
DESIGNS
Pin Description
Input - This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the isp state machine.
When ispEN is high, it functions as a dedicated input pin.
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2-0002-2096
PQFP & TQFP PIN NUMBERS
DESCRIPTION
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
18
46
78
15
19
50
20
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
64,
114
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
110
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
26
32
39
45
57
63
71
77
90
96
103
109
122
128
7
13
1,
97,
17,
112
33,
49,
16,
48,
82,
113
65,
81,
Global Output Enables input pins.
GOE 0, GOE 1
GND
VCC
VCC
Ground (GND)
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN0 also is used as one of the two control pins for the isp state
machine. When ispEN is high, it functions as a dedicated input pin.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
RESET
Y0, Y1, Y2
SDI/IN 02
ispEN
MODE/IN 12
51,
84,
80
83,
Dedicated input pins to the device.
IN 2, IN 4, IN 5
Output - When ispEN is logic low, it functions as an output pin to read
serial shift register data.
SDO
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
SCLK/IN 32
14,
47,
79,
111,
115,
116
No Connect.
NC1
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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