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參數(shù)資料
| 型號： | ISPLSI 2128E-180LT176 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 128I/O 5NS 176TQFP |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | ispLSI® 2000E |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 5.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 32 |
| 宏單元數(shù)： | 128 |
| 門數(shù)： | 6000 |
| 輸入/輸出數(shù)： | 128 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-TQFP（24x24） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI2128E-180LT176 |
Specifications ispLSI 2128E
2
Functional Block Diagram
Figure 1. ispLSI 2128E Functional Block Diagram
Global
Routing
Pool
(GRP)
0139/2128E
Megablock
RESET
Input Bus
D3
D2
D1
D0
D7
D6
D5
D4
Output Routing Pool (ORP)
I/O
127
I/O
126
I/O
125
I/O
124
I/O
123
I/O
122
I/O
121
I/O
120
I/O
119
I/O
118
I/O
117
I/O
116
I/O
115
I/O
114
I/O
113
I/O
112
I/O
111
I/O
110
I/O
109
I/O
108
I/O
107
I/O
106
I/O
105
I/O
104
I/O
103
I/O
102
I/O
101
I/O
100
I/O
99
I/O
98
I/O
97
I/O
96
TDI/IN
7
C7
C6
C5
C4
C3
C2
C1
C0
Output
Routing
Pool
(ORP)
Output
Routing
Pool
(ORP)
Input
Bus
IN 5
IN 4
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 95
I/O 94
I/O 93
I/O 92
Output Routing Pool (ORP)
Input Bus
CLK
0
I/O
32
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
Y0
Y1
Y2
IN
2
IN
3
B4
B5
B6
B7
B0
B1
B2
B3
Output
Routing
Pool
(ORP)
Output
Routing
Pool
(ORP)
A0
A1
A2
A3
A4
A5
A6
A7
BSCAN
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 0
I/O 1
I/O 2
I/O 3
GOE 0
GOE 1
CLK
1
CLK
2
Input
Bus
TCK/ IN 0
TMS/IN 1
TDO/IN
6
Generic Logic
Blocks (GLBs)
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise. By
connecting the VCCIO pins to a common 5V or 3.3V
power supply, I/O output levels can be matched to 5V or
3.3V compatible voltages. When connected to a 5V
supply, the I/O pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2128E device contains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2128E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2128E-180LT176 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2128V | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128V-60LJ84 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128V-60LJ84I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128V-60LQ160 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
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