參數(shù)資料
型號: ISPPAC-CLK5304S-01TN48I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 16/56頁
文件大?。?/td> 0K
描述: IC CLOCK PROGRAM BUFFER 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類型: 時鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/無
頻率 - 最大: 267MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
23
Figure 17. LVDS Input Receiver Conguration
Note that while a oating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry
may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-
put driver typically requires an external DC ‘pull-down’ path to a VTERM termination voltage (typically VCC-2V) to
properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5300S inter-
nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive
current. The pull-down should be implemented with external resistors placed close to the LVPECL driver
Figure 18. LVPECL Input Receiver Conguration
Please note that while the above discussions specify using 50Ω termination impedances, the actual impedance
required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The
REFA_REFP
REFB_REFN
Differential
Receiver
VTT_REFA
Close
VTT_REFB
Circ
u
it
Board
Connection
ispClock5300S
50
+
LVDS
Driver
Differential
Receiver
REFA-VTT
RPD
VTERM
REFB-VTT
Circ
u
it
Board
Connection
ispClock5300S
Close
50
+
LVPECL
Driver
REFA_REFP
REFB_REFN
相關(guān)PDF資料
PDF描述
X9401WV24T1 IC XDCP QUAD 64-TAP 10K 24-TSSOP
ADF4153YRUZ-RL IC SYNTH FRACT-N FREQ 16-TSSOP
VI-BTP-MV-S CONVERTER MOD DC/DC 13.8V 150W
X9401WV24IT1 IC XDCP QUAD 64-TAP 10K 24-TSSOP
X9401WV24I-2.7T1 IC XDCP QUAD 64-TAP 10K 24-TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5304S-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01TN64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5304S-01TN64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5308S-01T48C 功能描述:時鐘驅(qū)動器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5308S-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended