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參數(shù)資料
| 型號： | ISPPAC-CLK5304S-01TN48I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 29/56頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK PROGRAM BUFFER 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
35
Figure 30. PAC-Designer Design Entry Screen
In-System Programming
The ispClock5300S is an In-System Programmable (ISP) device. This is accomplished by integrating all
E
2CMOS conguration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant
serial JTAG interface at normal logic levels. Once a device is programmed, all conguration information is stored
on-chip, in non-volatile E
2CMOS memory cells. The specics of the IEEE 1149.1 serial interface and all
ispClock5300S instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
2CMOS memory of the ispClock5300S. This consists
of 32 bits that can be congured by the user to store unique data such as ID codes, revision numbers or inventory
control data. The specics this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispClock5300S device to prevent unauthorized readout
of the E
2CMOS conguration bit patterns. Once programmed, this cell prevents further access to the functional
user bits in the device. This cell can only be erased by reprogramming the device, so the original conguration can
not be examined once programmed. Usage of this feature is optional. The specics of this feature are discussed in
the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a nal conguration is determined, an ASCII format JEDEC le can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specic conguration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and exibility in production planning.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5304S-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01TN64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01TN64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5308S-01T48C | 功能描述:時(shí)鐘驅(qū)動器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5308S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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