參數(shù)資料
型號: ISPPAC-CLK5316S-01T64I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 40/56頁
文件大?。?/td> 0K
描述: IC BUFFER FANOUT ISP UNIV 64TQFP
標準包裝: 160
系列: ispClock™
類型: 時鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:16
差分 - 輸入:輸出: 是/無
頻率 - 最大: 267MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
45
GNDD
Digital GND
GND
18, 29, 30, 31,
62
29, 30, 62
REFA_REFP
Clock Reference A/ Positive Differential Input
3
Input
20
REFB_REFN
Clock Reference B/ Negative Differential Input
3
Input
21
REFSEL
Clock Reference Select input (LVCMOS)
Input
25
VTT_REFA
Termination voltage for reference input A
Power
19
FBK
Feedback input
3
Input
23
VTT_FBK
Termination voltage for feedback input
Power
24
VTT_REFB
Termination voltage for reference input B
Power
22
VCCJ
JTAG Interface VCC
Power
55
TDO
JTAG TDO output
Output
51
TDI
JTAG TDI input
Input
2
54
TCK
JTAG Clock input
Input
53
TMS
JTAG Mode select
Input
2
52
LOCK
PLL Lock indicator, HIGH indicates PLL Lock
Output
59
OEX
Output enable X
Input
1
57
OEY
Output enable Y
Input
1
56
PLL_BYPASS
PLL Bypass
Input
1
58
RESET
Reset PLL
Input
2
26
NC
No internal connection
N/A
15, 16, 17, 32,
33, 34
1. Internal pull-down resistor.
2. Internal pull-up resistor.
3. Must be connected to GNDD if not used.
Pin Descriptions – ispClock5316S, 5320S (Continued)
Pin Name
Description
Pin Type
ispClock5316S
64 TQFP
ispClock5320S
64 TQFP
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