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參數(shù)資料
| 型號： | IXDP631PI |
| 廠商： | IXYS |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 0K |
| 描述： | IC GENERATOR DGTL DEADTIME 8PDIP |
| 標(biāo)準包裝： | 21 |
| 應(yīng)用： | PWM 電機控制器 |
| 接口： | 微處理器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 18-DIP |
| 包裝： | 管件 |
| 安裝類型： | 通孔 |
I - 16
1998 IXYS All rights reserved
IXDP630
IXDP631
Sym. Pin Description
GND
9 CIRCUIT GROUND - 0 Volts
RCIN 10 The first node of the clock
or
network. For the IXDP630, the
XTLIN
RC input is applied to RCIN. For
the IXDP 631, the crystal oscil-
lator is applied to XTLIN. If an
external clock is to be supplied
to the chip it should be connec-
ted to this pin.
OSC 11 This is the output node of the
OUT
oscillator. It is connected indi-
rectly to the RCIN or XTLIN pins
when using the internal oscillator
as described in the applications
information. It is not recommen-
ded for external use.
TL
12 After the appropriate delay, the
TU
13 external drive outputs (R,S, T) U
SL
14 are in phase with their corres-
SU
15 ponding inputs; (R,S, T) L are
RL
16 the complementary outputs.
RU
17
V
CC
18 Voltage Supply +5 V ± 10 %
Sym. Pin Description
R
1 R, S and T are the three single-
S
3 phase inputs. Each input is
T
5 expanded into two outputs to
generate non-overlapping drive
signals, RU/RL, SU/SL, and TU/
TL. The delay from the falling
edge of one line to the rising
edge of the other is a function of
the clock.
ENAR 2 High logic input will enable the
ENAS 4 outputs, as set by the proper
ENAT 6 input phase. The ENA (R,S,T)
signals control the drive output
lines. A low logic input will force
both controlled outputs to a low
logic level
OUT 7 High logic level will enable all
ENA
outputs to their related phase.
The OUTENA simultaneously
controls all outputs. Low input
logic level will inhibit all outputs
(low).
RESET 8 The RESET signal is active low.
When a logic low RESET is
applied, all outputs will go low.
After releasing the RESET
command within the generated
delay, the outputs will align with
the phase input level after the
programmed delay internal.
Pin Description IXDP630
Pin Description IXDP631
Waveforms
deadtime
This diagram shows the normal
operation of the IXDP630/631 after the
RESET input is released. The
DEADTIME is the 8 Clock periods
between XU and XL when both XU and
XL are a "0". The length of the
DEADTIME is fixed at 8 times the
period of CLK.
Thediagram shows OUTENA and ENAX
asynchronously forcing the XU Output
and the XL Output to the off state.
OUTENA will force all three channels to
the off state. ENAX (where X is one of
the three channels) will only force the
XU and XL Outputs of that channel to
the off state. Note that because ENAX
is asynchronous with respect to the
internal clock and deadtime counters,
when ENAX goes HI whatever state the
deadtime counter was in immediately
propagates to the output. This figure
also shows that noise at the XIN input
will be filtered before the XU Output or
XL Output will become active, which
may extend the deadtime.
Note: X = Any input, R, S or T.
noise
deadtime
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