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參數(shù)資料
| 型號(hào)： | K3P6C2000B-SC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32M-Bit (2Mx16 /1Mx32) CMOS MASK ROM |
| 中文描述： | 32兆位（2Mx16 / 1Mx32）的CMOS掩膜ROM |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 63K |
| 代理商： | K3P6C2000B-SC |
K3P6C2000B-SC
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.6V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
0.8V and 2.0V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
°
C to 70
°
C, V
CC
=5V
±
10%, unless otherwise noted.)
READ CYCLE
NOTE
: Page Address is determined as below.
Double word mode (WORD=V
IH
) ; A
0
, A
1
Word mode (WORD=V
IL
) ; A
-1
, A
0
, A
1
Item
Symbol
K3P6C2000B-SC10
K3P6C2000B-SC12
K3P6C2000B-SC15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
150
ns
Chip Enable Access Time
t
ACE
100
120
150
ns
Address Access Time
t
AA
100
120
150
ns
Page Address Access Time
t
PA
30
50
70
ns
Output Enable Access Time
t
OE
30
50
70
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
30
ns
Output Hold from Address Change
t
OH
0
0
0
ns
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