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參數資料
| 型號： | K4C89083AF-GIF6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 288Mb x18 Network-DRAM2 Specification |
| 中文描述： | 288Mb x18網絡DRAM2規(guī)范 |
| 文件頁數： | 9/55頁 |
| 文件大?。?/td> | 1470K |
| 代理商： | K4C89083AF-GIF6 |
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K4C89183AF
DC Characteristics and Operating Conditions
(VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85
°
C)
- 9 -
REV. 0.7 Jan. 2005
Parameter
Symbol
Max
FB
Units
Notes
F6
F5
Operating Current
One bank Read or Write operation;
t
CK
= min, I
RC
= min, I
OUT
= 0mA;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V
≤
V
IN
≤
V
IL(AC)
(max.), V
IH(AC)
(min.)
≤
V
IN
≤
V
DDQ;
Address inputs change up to 2 times during minimum I
RC
,
Read data change twice per clock cycle
I
DD1S
320
300
280
mA
1, 2
Standby Current
All Banks : inactive state;
t
CK
=min, CS = V
IH
, PD = V
IH
;
0V
≤
V
IN
≤
V
IL
(AC)(max.), V
IH
(AC)(min.)
≤
V
IH
≤
V
DDQ;
Other input signals change one time during 4*t
CK,
DQ and DS inputs change twice per clock cycle
Standby (Power Down) Current
All Banks : inactive state;
t
CK
=min, PD = V
IL
(Power Down);
CAS Latency = 6, Free running QS mode;
0V
≤
V
IN
≤
V
IL
(AC)(max), V
IH
(AC)(min)
≤
V
IN
≤
V
DDQ
;
Other input signals change one time during 4*t
CK
,
DQ and DS inputs are floating(V
DDQ
/2)
Write Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
t
CK
= min, I
RC
= min;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V
≤
V
IN
≤
V
IL
(AC) (max.), V
IH
(AC)(min.)
≤
V
IN
≤
V
DDQ;
Address inputs change once per clock cycle,
DQ and DS inputs change twice per clock cycle
I
DD2N
100
95
90
1
I
DD2P
70
65
60
1
I
DD4W
650
600
550
1
Read Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
t
CK
= min, I
RC
= min, I
OUT
= 0mA;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V
≤
V
IN
≤
V
IL
(AC) (max.), V
IH
(AC)(min.)
≤
V
IN
≤
V
DDQ;
Address inputs change once per clock cycle,
Read data change twice per clock cycle
Burst Auto-Refresh Current
Refresh command at every I
REFC
interval;
t
CK
= min, I
REFC
= min;
CAS Latency = 6, Free running QS mode;
0V
≤
V
IN
≤
V
IL
(AC) (max.), V
IH
(AC) (min.)
≤
V
IN
≤
V
DDQ;
Address change up to 2 times during minimum I
REFC
,
DQ and DS inputs change twice per clock cycle
I
DD4R
650
600
550
1,2
I
DD5B
250
235
210
1,3
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