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K4C89183AF
- 12 -
REV. 0.7 Jan. 2005
AC Characteristics and Operating Conditions
(Notes : 1, 2) (Continued)
Symbol
Parameter
F6
FB
F5
Units Notes
Min
Max
Min
Max
Min
Max
t
LZ
Data-out Low Impedance Time from CLK
-0.5
-
-0.5
-
-0.6
-
3, 6, 8
t
HZ
Data-out High Impedance Time from CLK
-
0.5
-
0.5
-
0.6
3, 7, 8
t
QPDH
Last Output to PD High Hold Time
0
-
0
-
0
-
t
PDEX
Power Down Exit Time
0.6
-
0.6
-
0.7
-
3
t
T
Input Transition Time
0.1
1
0.1
1
0.1
1
t
FPDL
PD Low Input Window for Self-Refresh Entry
-0.5*t
CK
5
-0.5*t
CK
5
-0.5*t
CK
5
3
t
REFI
Auto-Refresh Average Interval
0.4
3.9
0.4
3.9
0.4
3.9
us
5
t
PAUSE
Pause Time after Power-up
200
-
200
-
200
-
I
RC
Random Read/Write Cycle Time
(Applicable to Same Bank)
C
L
= 4
5
-
5
-
5
-
Cycle
C
L
= 5
6
-
6
-
6
-
C
L
= 6
7
-
7
-
7
-
C
L
= 7
-
-
-
-
-
-
I
RCD
RDA/WRA to LAL Command Input Delay
(Applicable to Same Bank)
1
1
1
1
1
1
I
RAS
LAL to RDA/WRA Command Input Delay
(Applicable to Same Bank)
C
L
= 4
4
-
4
-
4
-
C
L
= 5
5
-
5
-
5
-
C
L
= 6
6
-
6
-
6
-
C
L
= 7
-
-
-
-
-
-
I
RBD
Random Bank Access Delay
(Applicable to Other Bank)
2
-
2
-
2
-
I
RWD
LAL following RDA to WRA Delay
(Applicable to Other Bank)
BL = 4
3
-
3
-
3
-
I
WRD
LAL following WRA to RDA Delay
(Applicable to Other Bank)
1
-
1
-
1
-
I
RSC
Mode Register Set Cycle Time
C
L
= 4
7
-
7
-
7
-
C
L
= 5
7
-
7
-
7
-
C
L
= 6
7
-
7
-
7
-
C
L
= 7
I
PD
PD Low to Inactive State of Input Buffer
-
2
-
2
-
2
I
PDA
PD High to Active State of Input Buffer
1
-
1
-
1
-
I
PDV
Power down mode valid from REF com-
mand
C
L
= 4
19
-
19
-
19
-
C
L
= 5
23
-
23
-
23
-
C
L
= 6
25
-
25
-
25
-
C
L
= 7
I
REFC
Auto-Refresh Cycle Time
C
L
= 4
19
-
19
-
19
-
C
L
= 5
23
-
23
-
23
-
C
L
= 6
25
-
25
-
25
-
C
L
= 7
I
LOCK
DLL Lock-on Time (Applicable to RDA command)
200
-
200
-
200
-
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| K4C89163AF-GIF5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
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| K4C89183AF | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
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