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參數(shù)資料
| 型號(hào)： | K4C89183AF-AIF6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | JT 55C 55#22M PIN PLUG |
| 中文描述： | 288Mb x18網(wǎng)絡(luò)DRAM2規(guī)范 |
| 文件頁數(shù)： | 48/55頁 |
| 文件大?。?/td> | 1470K |
| 代理商： | K4C89183AF-AIF6 |
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K4C89183AF
- 48 -
REV. 0.7 Jan. 2005
Function Description
Network - DRAM
Network - DRAM is an acronym of Double Data Rate Network - DRAM.
Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.
Pin Functions
Clock Inputs : CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all
address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK. The QS and DQ output
data are aligned to the crossing point of CLK and CLK. The timing reference point for the differential clock is when the CLK and CLK
signals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like
a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being per-
formed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided
by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for
the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS).
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank
address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs
are also used for setting the data in the Regular or Extended Mode Register set cycle.
BA0
BA1
Bank #0
Bank #1
0
1
0
0
Bank #2
0
1
Bank #3
1
1
Upper Address
A0 to A14
Lower Address
A0 to A6
K4C89183AF
相關(guān)PDF資料 |
PDF描述 |
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| K4C89083AF-AIFB | JT 55C 55#22 SKT PLUG |
| K4C89093AF-AIFB | 288Mb x18 Network-DRAM2 Specification |
| K4C89163AF-AIFB | JT 8C 8#16 PIN PLUG |
| K4C89183AF-AIFB | 288Mb x18 Network-DRAM2 Specification |
| K4C89083AF-GIFB | 288Mb x18 Network-DRAM2 Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4C89183AF-AIFB | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
| K4C89183AF-GCF5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
| K4C89183AF-GCF6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
| K4C89183AF-GCFB | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
| K4C89183AF-GIF5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
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