參數(shù)資料
型號: K4C89183AF-GIFB
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 288Mb x18 Network-DRAM2 Specification
中文描述: 288Mb x18網(wǎng)絡(luò)DRAM2規(guī)范
文件頁數(shù): 52/55頁
文件大小: 1470K
代理商: K4C89183AF-GIFB
K4C89183AF
- 52 -
REV. 0.7 Jan. 2005
RDA
LAL
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode
Data
Data 0
Data 1
Data 2
Data 3
Access Address
n
n + 1
n + 2
n + 3
Burst Length
4 words(Address bits is LA1, LA0)
not carried from LA1~LA2
CAS Latency = 4 (Free Running QS mode)
CK
CK
Command
QS
DQ
Functional Description (Continued)
Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
Data
Data 0
Data 1
Data 2
Data 3
Access Address
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Burst Length
4 words
Addressing sequence for Interleave mode
A6
0
A5
0
A4
0
CAS
Latency
Reserved
0
0
0
1
1
0
Reserved
Reserved
0
1
1
Reserved
1
1
0
0
0
1
4
5
1
1
0
6
1
1
1
7
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