- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄373060 > K4D263238F (SAMSUNG SEMICONDUCTOR CO. LTD.) 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL PDF資料下載
參數(shù)資料
| 型號(hào)： | K4D263238F |
| 廠(chǎng)商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| 中文描述： | 100萬(wàn)x 32Bit的× 4銀行雙數(shù)據(jù)速率同步DRAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大小： | 237K |
| 代理商： | K4D263238F |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
128M DDR SDRAM
K4D263238F
- 9 -
Rev 1.1 (May 2003)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The
default value of the extended mode register is not defined, therefore the extend mode register must be written after power
up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high
on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going
low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped-
ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
A
0
0
1
DLL Enable
Enable
Disable
BA
0
0
1
A
n
~ A
0
MRS
EMRS
Figure 7. Extend Mode Register set
EXTENDED MODE REGISTER SET(EMRS)
Address Bus
Extended
Mode Register
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
RFU
1
RFU
D.I.C
RFU
D.I.C
DLL
* RFU(Reserved for future use)
should stay "0" during EMRS
cycle.
A
6
0
1
A
1
1
1
Output Driver Impedance Control
Weak
Matched
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4D263238F-QC50 | 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| K4D263238F-QC40 | 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| K4D28163HD-TC36 | 128Mbit DDR SDRAM |
| K4D28163HD-TC40 | 128Mbit DDR SDRAM |
| K4D28163HD-TC50 | 128Mbit DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D263238F-QC40 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| K4D263238F-QC50 | 制造商:Samsung Electro-Mechanics 功能描述:4M X 32 DDR DRAM, 0.7 ns, PQFP100 |
| K4D263238F-QC50000 | 制造商:Samsung 功能描述:DDR SGRAM X32 TQFP - Trays |
| K4D263238G-GC | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
| K4D263238G-GC2A | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。