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參數資料
| 型號： | K4D64163HF |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| 中文描述： | 100萬× 16 × 4，銀行雙數據速率同步DRAM |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 162K |
| 代理商： | K4D64163HF |
64M DDR SDRAM
K4D64163HF
- 5 -
Rev. 1.1(Aug. 2002)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
’
s and DM
’
s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
LDQS,(U)DQS
Input/Output
Data Strobe : Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ;
UDQS corresponds to the data on DQ8-DQ15.
LDM,UDM
Input
Input Data Mask : DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS. DM
pins include dummy loading internally, to matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ;
UDM correspons to the data on DQ8-DQ15.
DQ
0
~ DQ
15
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Selects which bank is to be active.
A
0
~ A
11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
7
.
V
DD
/V
SS
Power Supply
Power and ground for the input buffers and core logic.
V
DDQ
/V
SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
V
REF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
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| K4D64163HF-TC33 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC36 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC40 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
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| K4D64163HF-TC60 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| K4D64163HF-TC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC36 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
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