參數(shù)資料
型號(hào): K4H560838D-TLB0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128Mb DDR SDRAM
中文描述: 128MB DDR SDRAM的
文件頁(yè)數(shù): 12/19頁(yè)
文件大?。?/td> 171K
代理商: K4H560838D-TLB0
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
相關(guān)PDF資料
PDF描述
K4H560838E-NLA2 256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)
K4H560838E-NLB0 10-Bit, 32 kSPS ADC Serial Out, uProcessor Periph./Standalone, 11 Ch. 20-SOIC
K4H560838E-NLB3 256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)
K4H560838E-TCA0 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-SOIC
K4H560838E-TCA2 128Mb DDR SDRAM
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