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參數(shù)資料
| 型號(hào)： | K4H560838E-NLA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| 中文描述： | 256Mb的電子芯片DDR SDRAM內(nèi)存規(guī)格54pin sTSOP（二） |
| 文件頁(yè)數(shù)： | 19/19頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | K4H560838E-NLA2 |
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DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H560838E-NLB0 | 10-Bit, 32 kSPS ADC Serial Out, uProcessor Periph./Standalone, 11 Ch. 20-SOIC |
| K4H560838E-NLB3 | 256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| K4H560838E-TCA0 | 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-SOIC |
| K4H560838E-TCA2 | 128Mb DDR SDRAM |
| K4H560838E-TCB0 | 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H560838E-NLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| K4H560838E-NLB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| K4H560838E-TC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 66 TSOP-II |
| K4H560838E-TC/LAA | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 66 TSOP-II |
| K4H560838E-TC/LB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 66 TSOP-II |
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