參數(shù)資料
型號: K4S161622H-TC60
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 16Mb H-die SDRAM Specification
中文描述: 16Mb的?芯片內(nèi)存規(guī)格
文件頁數(shù): 10/11頁
文件大?。?/td> 108K
代理商: K4S161622H-TC60
SDRAM 16Mb H-die(x16)
CMOS SDRAM
Rev. 1.5 August 2004
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Parameters depend on programmed CAS latency.
6. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
7. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
8. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
(AC operating conditions unless otherwise noted)
Parameter
Symbol
55
60
-70
-80
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
CC
5.5
1000
6
1000
7
1000
8
1000
ns
5
CAS Latency=2
10
10
10
10
CLK to valid
output delay
CAS Latency=3
t
SAC
-
5
-
5.5
-
5.5
-
6
ns
5, 6
CAS Latency=2
-
6
-
6
-
6
-
6
Output data
t
OH
2
-
2.5
-
2.5
-
2.5
-
ns
6
CLK high pulse
width
CAS Latency=3
t
CH
2
-
2.5
-
3
-
3
-
ns
7
CAS Latency=2
3
3
CLK low pulse
width
CAS Latency=3
t
CL
2
-
2.5
-
3
-
3
-
ns
7
CAS Latency=2
3
3
Input setup time
CAS Latency=3
t
SS
1.5
-
1.5
-
1.75
-
2
-
ns
7
CAS Latency=2
2
2
2
Input hold time
t
SH
1
-
1
-
1
-
1
-
ns
7
CLK to output in Low-Z
t
SLZ
1
-
1
-
1
-
1
-
ns
6
CLK to output
in Hi-Z
CAS Latency=3
t
SHZ
-
5
-
5.5
-
5.5
-
6
ns
CAS Latency=2
-
6
-
6
-
6
-
6
Notes :
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