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參數(shù)資料
| 型號： | K4S1G0732B-TC75 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SDRAM stacked 1Gb B-die |
| 中文描述： | 1Gb的乙堆疊內(nèi)存芯片 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 126K |
| 代理商： | K4S1G0732B-TC75 |
CMOS SDRAM
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
PIN CONFIGURATION
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
V
DD
DQ0
V
DDQ
N.C
DQ1
V
SSQ
N.C
DQ2
V
DDQ
N.C
DQ3
V
SSQ
N.C
V
DD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
SS
DQ7
V
SSQ
N.C
DQ6
V
DDQ
N.C
DQ5
V
SSQ
N.C
DQ4
V
DDQ
N.C
V
SS
CKE1
DQM
CLK
CKE0
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CS0~1
Chip select
CKE0~1
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A
0
~ A
12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
12
, Column address : CA
0
~ CA
9,
CA
11
BA
0
~ BA
1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
DQ
0
~
7
V
DD
/V
SS
Data input/output
Power supply/ground
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V
DDQ
/V
SSQ
Data output power/ground
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