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參數(shù)資料
| 型號(hào)： | K4S643232H-TC55 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Mb H-die (x32) SDRAM Specification |
| 中文描述： | 64兆?芯片（X32號(hào)）內(nèi)存規(guī)格 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 118K |
| 代理商： | K4S643232H-TC55 |
CMOS SDRAM
- 10
SDRAM 64Mb H-die (x32)
Rev. 1.4 August 2004
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
30pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
30pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
50
55
60
70
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS
t
CC
5
1000
5.5
1000
6
1000
7
1000
ns
1
CAS
10
10
10
10
Row active to row active delay
RAS to CAS delay
Row precharge time
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
2
CLK
CLK
CLK
CLK
us
1
1
1
1
3
3
8
2
2
5
3
3
7
2
2
5
3
3
7
2
2
5
3
3
7
2
2
5
Row active time
100
Row cycle time
t
RC
(
min
)
11
7
10
7
10
7
10
7
CLK
1
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
t
RDL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
t
MRS(min)
2
1
1
1
2
2
1
CLK
CLK
CLK
CLK
CLK
2
2
2
3
Number of valid
output data
CAS Latency=3
CAS Latency=2
ea
4
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