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參數(shù)資料
| 型號(hào)： | K6T0808C1D-TL70 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx8 bit Low Power CMOS Static RAM |
| 中文描述： | 32Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | K6T0808C1D-TL70 |
K6T0808C1D Family
CMOS SRAM
Revision 1.0
November 1997
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
CS
tWC
tWR(4)
tAS(3)
tDW
tDH
Data Valid
WE
Data in
Data out
High-Z
tCW(2)
tWP(1)
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC
4.5V
2.2V
VDR
CS
GND
Data Retention Mode
CS
≥VCC - 0.2V
tSDR
tRDR
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS
tCW(2)
tWR(4)
tWP(1)
tDW
tDH
tOW
tWHZ
Data Undefined
Data Valid
WE
Data in
Data out
tWC
tAW
tAS(3)
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| K6T0808C1D-TP70 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:32Kx8 bit Low Power CMOS Static RAM |
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