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參數(shù)資料
| 型號： | K7B321825M-QC65 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | DRAM |
| 英文描述： | 1Mx36 & 2Mx18 Synchronous SRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 247K |
| 代理商： | K7B321825M-QC65 |
1Mx36 & 2Mx18 Synchronous SRAM
- 17 -
Rev 2.0
Nov. 2003
K7A321800M
K7A323600M
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
Data
Address
CLK
ADS
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
1Mx18
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
1Mx18
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:20]
A
[20]
A
[0:19]
A
[20]
A
[0:19]
I/O
[0:71]
Clock
ADSP
ADDRESS
[0:n]
Data Out
(Bank 0)
Bank 0 is selected by
CS
2
, and Bank 1 deselected by
CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
(Bank 1)
t
SS
tSH
Don
′
t Care
A1
A2
WRITE
CS
1
A
n+1
ADV
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
tHZC
Bank 0 is deselected by
CS
2
, and Bank 1 selected by
CS
2
t
CSS
tCSH
t
CD
t
LZC
Undefined
Q2-1
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
*Notes :
n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
20 2M depth
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| K7B321825M-QC75 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Synchronous SRAM |
| K7B321835C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Synchronous SRAM |
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| K7B323625M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Synchronous SRAM |
| K7B323625M-QC65 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Synchronous SRAM |
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