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參數(shù)資料
| 型號： | K7I161882B-FC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| 中文描述： | 512Kx36位，1Mx18位首席信息官b2條DDRII的SRAM |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 378K |
| 代理商： | K7I161882B-FC25 |
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
- 13 -
Rev 3.1
July. 2004
K7I163682B
K7I161882B
NOTE
1. Q
01
refers to output from address A. Q
02
refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after a NOP .
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent
bus contention.
TIMING WAVE FORMS OF READ, WRITE AND NOP
NOP
K
K
SA
CQ
1
2
3
4
5
6
7
8
10
12
11
LD
CQ
READ
(burst of 2)
(burst of 2)
WRITE
(burst of 2)
READ
9
READ
(burst of 2)
t
IVKH
t
KHKH
UNDEFINED
DON
′
T CARE
t
KHKH
t
KLKH
R/W
t
KHIX
C
C
NOP
(Note3)
t
KHKL
t
KHKH
t
KHKL
t
KLKH
t
KHKH
DQ
D
31
D
41
D
42
D
32
A
2
Q
01
Q
02
Q
11
Q
12
Q
21
Q
22
A
0
Q
51
Q
52
Q
61
A
1
A
5
A
3
A
4
A
6
Q
62
READ
(burst of 2)
NOP
(burst of 2)
WRITE
READ
(burst of 2)
NOP
NOP
t
KHCH
t
CHQV
t
CHQX1
t
CHCQX
t
CHCQV
t
CHQX
t
CHQZ
t
KHDX
t
DVKH
t
CHQV
t
CHCQX
t
CHCQV
相關(guān)PDF資料 |
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| K7I161882B-FC30 | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
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| K7I163682B-FC16 | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| K7I163682B-FC20 | GT 35C 35#16 PIN PLUG RTANG |
| K7I163682B-FC25 | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7I161882B-FC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| K7I161884B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDRII CIO b4 SRAM |
| K7I161884B-FC25T00 | 制造商:Samsung Semiconductor 功能描述:16MSYNC DDRII, COMMON I/O SRAM 1MX18FBGA, T/R - Tape and Reel |
| K7I163682B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| K7I163682B_06 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDRII CIO b2 SRAM |
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