參數(shù)資料
型號(hào)： K7I641884M
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 72Mb DDRII SRAM Specification
中文描述： 72Mb SRAM的規(guī)范條DDRII
文件頁(yè)數(shù)： 11/18頁(yè)
文件大?。?/td> 424K
代理商： K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
K7I643684M
K7I641884M
- 11 -
Rev. 1.3 March 2007
AC ELECTRICAL CHARACTERISTICS
(V
DD
=1.8V
±
0.1V, T
A
=0
°
C to +70
°
C)
Notes:
1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transition edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, V
IL(AC)
or V
IH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, V
IL(DC)
or V
IH(DC)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTES
Input High Voltage
V
IH
(AC)
V
REF
+ 0.2
-
V
1,2
Input Low Voltage
V
IL
(AC)
-
V
REF
- 0.2
V
1,2
AC TIMING CHARACTERISTICS
(V
DD
=1.8V
±
0.1V, T
A
=0
°
C to +70
°
C)
Notes
: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW
0
,BW
1
and BW
2
, BW
3
, also for x36
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
1
is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX
1
is a MIN parameter that is worst case at totally different test conditions
(0
°
C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70
°
C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a
± 0.1
ns variation from echo clock to data.
The data sheet parameters reflect tester guard bands and test setup variations.
PARAMETER
SYMBOL
-30
-25
-20
-16
UNIT NOTE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time (K, K, C, C)
t
KHKH
3.30
8.40
4.00
8.40
5.00
8.40
6.00
8.40
ns
Clock Phase Jitter (K, K, C, C)
t
KC var
0.20
0.20
0.20
0.20
ns
5
Clock High Time (K, K, C, C)
t
KHKL
1.32
1.60
2.00
2.40
ns
Clock Low Time (K, K, C, C)
t
KLKH
1.32
1.60
2.00
2.40
ns
Clock to Clock (K
↑ →
K
↑
, C
↑
→
C
↑
)
t
KHKH
1.49
1.80
2.20
2.70
ns
Clock to data clock (K
↑ →
C
↑
, K
↑→
C
↑
)
t
KHCH
0.00
1.45
0.00
1.80
0.00
2.30
0.00
2.80
ns
DLL Lock Time (K, C)
t
KC lock
1024
1024
1024
1024
cycle
6
K Static to DLL reset
t
KC reset
30
30
30
30
ns
Output Times
C, C High to Output Valid
t
CHQV
0.45
0.45
0.45
0.50
ns
3
C, C High to Output Hold
t
CHQX
-0.45
-0.45
-0.45
-0.50
ns
3
C, C High to Echo Clock Valid
t
CHCQV
0.45
0.45
0.45
0.50
ns
C, C High to Echo Clock Hold
t
CHCQX
-0.45
-0.45
-0.45
-0.50
ns
CQ, CQ High to Output Valid
t
CQHQV
0.27
0.30
0.35
0.40
ns
7
CQ, CQ High to Output Hold
t
CQHQX
-0.27
-0.30
-0.35
-0.40
ns
7
C, High to Output High-Z
t
CHQZ
0.45
0.45
0.45
0.50
ns
3
C, High to Output Low-Z
t
CHQX1
-0.45
-0.45
-0.45
-0.50
ns
3
Setup Times
Address valid to K rising edge
t
AVKH
0.40
0.50
0.60
0.70
ns
Control inputs valid to K rising edge
t
IVKH
0.40
0.50
0.60
0.70
ns
2
Data-in valid to K, K rising edge
t
DVKH
0.30
0.35
0.40
0.50
ns
Hold Times
K rising edge to address hold
t
KHAX
0.40
0.50
0.60
0.70
ns
K rising edge to control inputs hold
t
KHIX
0.40
0.50
0.60
0.70
ns
K, K rising edge to data-in hold
t
KHDX
0.30
0.35
0.40
0.50
ns
相關(guān)PDF資料
PDF描述
K7I641884M-CE25 72Mb DDRII SRAM Specification
K7I641884M-CE30 72Mb DDRII SRAM Specification
K7I641884M-CI25 72Mb DDRII SRAM Specification
K7I641884M-CI30 72Mb DDRII SRAM Specification
K7I641884M-FC16 72Mb DDRII SRAM Specification
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K7I641884M-CE25 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I641884M-CE30 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I641884M-CI25 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I641884M-CI30 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
K7I641884M-FC16 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*