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參數(shù)資料
| 型號： | K7N323601M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18-Bit Pipelined NtRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 277K |
| 代理商： | K7N323601M |
1Mx36 & 2Mx18 Pipelined N
t
RAM
TM
- 17 -
Rev 2.0
Nov. 2003
K7N321801M
K7N323601M
JTAG DC OPERATING CONDITIONS
NOTE
: The input level of SRAM pin is to follow the SRAM DC specification
.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
V
DD
3.135
3.3
3.465
V
Input High Level ( 3.3V I/O / 2.5V I/O )
V
IH
2.0 / 1.7
-
V
DD
+0.3
V
Input Low Level ( 3.3V I/O / 2.5V I/O )
V
IL
-0.3
-
0.8 / 0.7
V
Output High Voltage( 3.3V I/O / 2.5V I/O )
V
OH
2.4 / 2.0
-
-
V
Output Low Voltage( 3.3V I/O / 2.5V I/O )
V
OL
-
-
0.4 / 0.4
V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
Note
TCK Cycle Time
t
CHCH
50
-
ns
TCK High Pulse Width
t
CHCL
20
-
ns
TCK Low Pulse Width
t
CLCH
20
-
ns
TMS Input Setup Time
t
MVCH
5
-
ns
TMS Input Hold Time
t
CHMX
5
-
ns
TDI Input Setup Time
t
DVCH
5
-
ns
TDI Input Hold Time
t
CHDX
5
-
ns
SRAM Input Setup Time
t
SVCH
5
-
ns
SRAM Input Hold Time
t
CHSX
5
-
ns
Clock Low to Output Valid
t
CLQV
0
10
ns
JTAG AC TEST CONDITIONS
Parameter
Symbol
Min
Unit
Note
Input High/Low Level( 3.3V I/O , 2.5V I/O )
V
IH
/V
IL
3.0/0 , 2.5/0
V
Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )
TR/TF
1.0/1.0 , 1.0/1.0
ns
Input and Output Timing Reference Level
V
DDQ
/2
V
TCK
TMS
TDI
PI
(SRAM)
t
CHCH
t
MVCH
t
CHMX
t
CHCL
t
CLCH
t
DVCH
t
CHDX
t
CLQV
TDO
t
SVCH
t
CHSX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7N323601M-FC13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Pipelined NtRAM |
| K7N323601M-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Pipelined NtRAM |
| K7N323601M-FC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Pipelined NtRAM |
| K7N323601M-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Pipelined NtRAM |
| K7N323601M-QC13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Pipelined NtRAM |
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